A 160MHz 4-bit pipeline multiplier using charge recovery logic technology

Yimeng Zhang, Leona Okamura, Nan Wang, Tsutomu Yoshihara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle.

    Original languageEnglish
    Title of host publication2010 International SoC Design Conference, ISOCC 2010
    Pages127-130
    Number of pages4
    DOIs
    Publication statusPublished - 2010
    Event2010 International SoC Design Conference, ISOCC 2010 - Incheon
    Duration: 2010 Nov 222010 Nov 23

    Other

    Other2010 International SoC Design Conference, ISOCC 2010
    CityIncheon
    Period10/11/2210/11/23

    Fingerprint

    Energy dissipation
    Pipelines
    Recovery
    Clocks
    Transistors

    ASJC Scopus subject areas

    • Hardware and Architecture

    Cite this

    Zhang, Y., Okamura, L., Wang, N., & Yoshihara, T. (2010). A 160MHz 4-bit pipeline multiplier using charge recovery logic technology. In 2010 International SoC Design Conference, ISOCC 2010 (pp. 127-130). [5682955] https://doi.org/10.1109/SOCDC.2010.5682955

    A 160MHz 4-bit pipeline multiplier using charge recovery logic technology. / Zhang, Yimeng; Okamura, Leona; Wang, Nan; Yoshihara, Tsutomu.

    2010 International SoC Design Conference, ISOCC 2010. 2010. p. 127-130 5682955.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Zhang, Y, Okamura, L, Wang, N & Yoshihara, T 2010, A 160MHz 4-bit pipeline multiplier using charge recovery logic technology. in 2010 International SoC Design Conference, ISOCC 2010., 5682955, pp. 127-130, 2010 International SoC Design Conference, ISOCC 2010, Incheon, 10/11/22. https://doi.org/10.1109/SOCDC.2010.5682955
    Zhang Y, Okamura L, Wang N, Yoshihara T. A 160MHz 4-bit pipeline multiplier using charge recovery logic technology. In 2010 International SoC Design Conference, ISOCC 2010. 2010. p. 127-130. 5682955 https://doi.org/10.1109/SOCDC.2010.5682955
    Zhang, Yimeng ; Okamura, Leona ; Wang, Nan ; Yoshihara, Tsutomu. / A 160MHz 4-bit pipeline multiplier using charge recovery logic technology. 2010 International SoC Design Conference, ISOCC 2010. 2010. pp. 127-130
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