A 1991 Mpixels/s intra prediction architecture for Super Hi-Vision H.264/AVC encoder

Gang He; Dajiang Zhou; Jinjia Zhou; Satoshi Goto

A 1991 Mpixels/s intra prediction architecture for Super Hi-Vision H.264/AVC encoder

Gang He^*, Dajiang Zhou, Jinjia Zhou, Satoshi Goto

^*Corresponding author for this work

Information, Production and Systems Research Center

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents an H.264/AVC intra prediction design for Super Hi-Vision (SHV) video. Due to huge throughput requirements, design challenges such as data dependency and complexity become even more critical. To solve these problems, we first propose an interlaced block reordering scheme together with a coarse-to-fine mode decision (CFMD) strategy to resolve the data dependency between intra mode decision and reconstruction. Circuits area is reduced in the meantime with CFMD. We also propose a probability-based reconstruction scheme to solve the problem from long pipeline latency. As a result, hardware complexity in terms of the product of area and frequency is reduced by 74%. The maximum throughput reaches 1991Mpixels/s for 7680×4320p 60fps video. Total logic gate count is 451.5k in 65nm library.

Original language	English
Title of host publication	European Signal Processing Conference
Pages	1054-1058
Number of pages	5
Publication status	Published - 2012
Event	20th European Signal Processing Conference, EUSIPCO 2012 - Bucharest Duration: 2012 Aug 27 → 2012 Aug 31

Other

Other	20th European Signal Processing Conference, EUSIPCO 2012
City	Bucharest
Period	12/8/27 → 12/8/31

Keywords

H.264/AVC
hardware architecture
intra prediction
SHV

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering

Cite this

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title = "A 1991 Mpixels/s intra prediction architecture for Super Hi-Vision H.264/AVC encoder",

abstract = "This paper presents an H.264/AVC intra prediction design for Super Hi-Vision (SHV) video. Due to huge throughput requirements, design challenges such as data dependency and complexity become even more critical. To solve these problems, we first propose an interlaced block reordering scheme together with a coarse-to-fine mode decision (CFMD) strategy to resolve the data dependency between intra mode decision and reconstruction. Circuits area is reduced in the meantime with CFMD. We also propose a probability-based reconstruction scheme to solve the problem from long pipeline latency. As a result, hardware complexity in terms of the product of area and frequency is reduced by 74%. The maximum throughput reaches 1991Mpixels/s for 7680×4320p 60fps video. Total logic gate count is 451.5k in 65nm library.",

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author = "Gang He and Dajiang Zhou and Jinjia Zhou and Satoshi Goto",

year = "2012",

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note = "20th European Signal Processing Conference, EUSIPCO 2012 ; Conference date: 27-08-2012 Through 31-08-2012",

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AU - He, Gang

AU - Zhou, Dajiang

AU - Zhou, Jinjia

AU - Goto, Satoshi

PY - 2012

Y1 - 2012

N2 - This paper presents an H.264/AVC intra prediction design for Super Hi-Vision (SHV) video. Due to huge throughput requirements, design challenges such as data dependency and complexity become even more critical. To solve these problems, we first propose an interlaced block reordering scheme together with a coarse-to-fine mode decision (CFMD) strategy to resolve the data dependency between intra mode decision and reconstruction. Circuits area is reduced in the meantime with CFMD. We also propose a probability-based reconstruction scheme to solve the problem from long pipeline latency. As a result, hardware complexity in terms of the product of area and frequency is reduced by 74%. The maximum throughput reaches 1991Mpixels/s for 7680×4320p 60fps video. Total logic gate count is 451.5k in 65nm library.

AB - This paper presents an H.264/AVC intra prediction design for Super Hi-Vision (SHV) video. Due to huge throughput requirements, design challenges such as data dependency and complexity become even more critical. To solve these problems, we first propose an interlaced block reordering scheme together with a coarse-to-fine mode decision (CFMD) strategy to resolve the data dependency between intra mode decision and reconstruction. Circuits area is reduced in the meantime with CFMD. We also propose a probability-based reconstruction scheme to solve the problem from long pipeline latency. As a result, hardware complexity in terms of the product of area and frequency is reduced by 74%. The maximum throughput reaches 1991Mpixels/s for 7680×4320p 60fps video. Total logic gate count is 451.5k in 65nm library.

KW - H.264/AVC

KW - hardware architecture

KW - intra prediction

KW - SHV

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M3 - Conference contribution

AN - SCOPUS:84869814808

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BT - European Signal Processing Conference

T2 - 20th European Signal Processing Conference, EUSIPCO 2012

Y2 - 27 August 2012 through 31 August 2012

ER -

A 1991 Mpixels/s intra prediction architecture for Super Hi-Vision H.264/AVC encoder

Abstract

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Keywords

ASJC Scopus subject areas

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