A 24-b 50-ns digital image signal processor

Shin ichi Nakagawa, Hideyuki Terane, Tetsuya Matsumura, Hiroshi Segawa, Hirofumi Shinohara, Hirofumi Shinohara, Shu ichi Kato, Masahiro Hatanaka, Hideo Ohira, Yoshiaki Kato, Mamoru Iwatsuki, Kinya Tabuchi, Yasutaka Horiba

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

A 50-ns digital image signal processor (DISP)--an image/video application-specific VLSI chip--is discussed. This chip integrates 538 K transistors and dissipates 1.4 W at a 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and an instruction cycle time that is typically 35 ns, and 50 ns at worst. This 50-ns cycle time allows the DISP to execute more than 60-million operations per second (MOPS). High-density 1.0-μm CMOS technology allows numerous on-chip features, including specified resources optimized for image processing. This allows a flexible hardware implementation of various algorithms for picture coding. Several circuit design techniques that are intended to attain a fast instruction cycle are reviewed, including distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with a cell-based design environment.

Original languageEnglish
Pages (from-to)1484-1493
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume25
Issue number6
DOIs
Publication statusPublished - 1990 Dec
Externally publishedYes

Fingerprint

Parallel architectures
Networks (circuits)
Decoding
Clocks
Transistors
Image processing
Pipelines
Hardware
Testing
Processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Nakagawa, S. I., Terane, H., Matsumura, T., Segawa, H., Shinohara, H., Shinohara, H., ... Horiba, Y. (1990). A 24-b 50-ns digital image signal processor. IEEE Journal of Solid-State Circuits, 25(6), 1484-1493. https://doi.org/10.1109/4.62184

A 24-b 50-ns digital image signal processor. / Nakagawa, Shin ichi; Terane, Hideyuki; Matsumura, Tetsuya; Segawa, Hiroshi; Shinohara, Hirofumi; Shinohara, Hirofumi; Kato, Shu ichi; Hatanaka, Masahiro; Ohira, Hideo; Kato, Yoshiaki; Iwatsuki, Mamoru; Tabuchi, Kinya; Horiba, Yasutaka.

In: IEEE Journal of Solid-State Circuits, Vol. 25, No. 6, 12.1990, p. 1484-1493.

Research output: Contribution to journalArticle

Nakagawa, SI, Terane, H, Matsumura, T, Segawa, H, Shinohara, H, Shinohara, H, Kato, SI, Hatanaka, M, Ohira, H, Kato, Y, Iwatsuki, M, Tabuchi, K & Horiba, Y 1990, 'A 24-b 50-ns digital image signal processor', IEEE Journal of Solid-State Circuits, vol. 25, no. 6, pp. 1484-1493. https://doi.org/10.1109/4.62184
Nakagawa SI, Terane H, Matsumura T, Segawa H, Shinohara H, Shinohara H et al. A 24-b 50-ns digital image signal processor. IEEE Journal of Solid-State Circuits. 1990 Dec;25(6):1484-1493. https://doi.org/10.1109/4.62184
Nakagawa, Shin ichi ; Terane, Hideyuki ; Matsumura, Tetsuya ; Segawa, Hiroshi ; Shinohara, Hirofumi ; Shinohara, Hirofumi ; Kato, Shu ichi ; Hatanaka, Masahiro ; Ohira, Hideo ; Kato, Yoshiaki ; Iwatsuki, Mamoru ; Tabuchi, Kinya ; Horiba, Yasutaka. / A 24-b 50-ns digital image signal processor. In: IEEE Journal of Solid-State Circuits. 1990 ; Vol. 25, No. 6. pp. 1484-1493.
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