A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a highly linear 28-GHz band SOI CMOS power amplifier with an adaptive bias circuit for cascode MOSFET for next generation wireless communication. The power amplifier consists of a cascode MOSFET, the adaptive bias circuit and the input and output matching circuits. The power amplifier has exhibited a simulated output P1dB (1-dB gain compression point) of 19.2 dBm and a PAE of 39.0 %.

Original languageEnglish
Title of host publicationEDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-2
Number of pages2
Volume2017-January
ISBN (Electronic)9781538629079
DOIs
Publication statusPublished - 2017 Dec 1
Event13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017 - Hsinchu, Taiwan, Province of China
Duration: 2017 Oct 182017 Oct 20

Other

Other13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017
CountryTaiwan, Province of China
CityHsinchu
Period17/10/1817/10/20

Fingerprint

Power amplifiers
Networks (circuits)
Communication

Keywords

  • Adaptive bias circuit
  • Linear power amplifier
  • SOI CMOS

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Sato, H., Yanagisawa, M., & Yoshimasu, T. (2017). A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS. In EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits (Vol. 2017-January, pp. 1-2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2017.8126403

A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS. / Sato, Hiroya; Yanagisawa, Masao; Yoshimasu, Toshihiko.

EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits. Vol. 2017-January Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-2.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sato, H, Yanagisawa, M & Yoshimasu, T 2017, A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS. in EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits. vol. 2017-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-2, 13th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2017, Hsinchu, Taiwan, Province of China, 17/10/18. https://doi.org/10.1109/EDSSC.2017.8126403
Sato H, Yanagisawa M, Yoshimasu T. A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS. In EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits. Vol. 2017-January. Institute of Electrical and Electronics Engineers Inc. 2017. p. 1-2 https://doi.org/10.1109/EDSSC.2017.8126403
Sato, Hiroya ; Yanagisawa, Masao ; Yoshimasu, Toshihiko. / A 28-GHz band highly linear power amplifier with novel adaptive bias circuit for cascode MOSFET in 56-nm SOI CMOS. EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits. Vol. 2017-January Institute of Electrical and Electronics Engineers Inc., 2017. pp. 1-2
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