A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications

Dajiang Zhou, Jinjia Zhou, Jiayi Zhu, Peilin Liu, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Abstract

8Kx4K Super Hi-Vision (SHV) offers a significantly enhanced visual experience relative to 1080p, and is on its way to being the next digital TV standard. In addition, advanced 3DTV specifications involving a large number of camera views are targeted by emerging applications such as free-viewpoint TV (FTV). This paper presents a single-chip design that supports real-time H.264 decoding of SHV or up to 32 HD views. The design of the chip involved 3 key challenges: 1) Data dependencies of video coding algorithms restrict the degree of hardware parallelism. For SHV, each macroblock (MB) should be processed in less than 40 cycles at 300MHz, which is difficult to meet with a single pipeline; 2) due to the massive design and verification effort for video decoders, a scalable architecture that allows the maximum reuse of existing IP is desirable; and 3) the DRAM bandwidth requirements are always a bottleneck in high-throughput video decoders.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages224-225
Number of pages2
Volume55
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event59th International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, CA, United States
Duration: 2012 Feb 192012 Feb 23

Other

Other59th International Solid-State Circuits Conference, ISSCC 2012
CountryUnited States
CitySan Francisco, CA
Period12/2/1912/2/23

Fingerprint

Dynamic random access storage
Image coding
Decoding
Pipelines
Cameras
Throughput
Specifications
Hardware
Bandwidth

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Zhou, D., Zhou, J., Zhu, J., Liu, P., & Goto, S. (2012). A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 55, pp. 224-225). [6176985] https://doi.org/10.1109/ISSCC.2012.6176985

A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. / Zhou, Dajiang; Zhou, Jinjia; Zhu, Jiayi; Liu, Peilin; Goto, Satoshi.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 55 2012. p. 224-225 6176985.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhou, D, Zhou, J, Zhu, J, Liu, P & Goto, S 2012, A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 55, 6176985, pp. 224-225, 59th International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, United States, 12/2/19. https://doi.org/10.1109/ISSCC.2012.6176985
Zhou D, Zhou J, Zhu J, Liu P, Goto S. A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 55. 2012. p. 224-225. 6176985 https://doi.org/10.1109/ISSCC.2012.6176985
Zhou, Dajiang ; Zhou, Jinjia ; Zhu, Jiayi ; Liu, Peilin ; Goto, Satoshi. / A 2Gpixel/s H.264/AVC HP/MVC video decoder chip for Super Hi-Vision and 3DTV/FTV applications. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 55 2012. pp. 224-225
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