A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara

    Research output: Contribution to journalArticle

    13 Citations (Scopus)

    Abstract

    An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm2 16-Mb embedded DRAM macro is fabricated in 0.13 μm logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36% for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-μW data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.

    Original languageEnglish
    Pages (from-to)204-210
    Number of pages7
    JournalIEEE Journal of Solid-State Circuits
    Volume40
    Issue number1
    DOIs
    Publication statusPublished - 2005 Jan

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    Dynamic random access storage
    Macros
    Capacitors

    Keywords

    • CMOS memory integrated circuits
    • Embedded DRAM
    • Mobile applications
    • System-on-chip

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Morishita, F., Hayashi, I., Matsuoka, H., Takahashi, K., Shigeta, K., Gyohten, T., ... Yoshihara, T. (2005). A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. IEEE Journal of Solid-State Circuits, 40(1), 204-210. https://doi.org/10.1109/JSSC.2004.837986

    A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. / Morishita, Fukashi; Hayashi, Isamu; Matsuoka, Hideto; Takahashi, Kazuhiro; Shigeta, Kuniyasu; Gyohten, Takayuki; Niiro, Mitsutaka; Noda, Hideyuki; Okamoto, Mako; Hachisuka, Atsushi; Amo, Atsushi; Shinkawata, Hiroki; Kasaoka, Tatsuo; Dosaka, Katsumi; Arimoto, Kazutami; Fujishima, Kazuyasu; Anami, Kenji; Yoshihara, Tsutomu.

    In: IEEE Journal of Solid-State Circuits, Vol. 40, No. 1, 01.2005, p. 204-210.

    Research output: Contribution to journalArticle

    Morishita, F, Hayashi, I, Matsuoka, H, Takahashi, K, Shigeta, K, Gyohten, T, Niiro, M, Noda, H, Okamoto, M, Hachisuka, A, Amo, A, Shinkawata, H, Kasaoka, T, Dosaka, K, Arimoto, K, Fujishima, K, Anami, K & Yoshihara, T 2005, 'A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications', IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 204-210. https://doi.org/10.1109/JSSC.2004.837986
    Morishita, Fukashi ; Hayashi, Isamu ; Matsuoka, Hideto ; Takahashi, Kazuhiro ; Shigeta, Kuniyasu ; Gyohten, Takayuki ; Niiro, Mitsutaka ; Noda, Hideyuki ; Okamoto, Mako ; Hachisuka, Atsushi ; Amo, Atsushi ; Shinkawata, Hiroki ; Kasaoka, Tatsuo ; Dosaka, Katsumi ; Arimoto, Kazutami ; Fujishima, Kazuyasu ; Anami, Kenji ; Yoshihara, Tsutomu. / A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. In: IEEE Journal of Solid-State Circuits. 2005 ; Vol. 40, No. 1. pp. 204-210.
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    abstract = "An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm2 16-Mb embedded DRAM macro is fabricated in 0.13 μm logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36{\%} for an RC delay can be reduced to 3.8{\%} by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-μW data retention power is realized by using the PDDR mode, which is 5{\%} of conventional schemes.",
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    AU - Kasaoka, Tatsuo

    AU - Dosaka, Katsumi

    AU - Arimoto, Kazutami

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