A 333MHz random cycle DRAM using the floating body cell

Kosuke Hatsuda*, Katsuyuki Fujita, Takashi Ohsawa

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

A Monte Carlo simulation shows that a DRAM using the floating body cell (FBC) realizes a 333MHz high-speed random cycle with an introduction of a symmetrical sense amplifier circuit and optimization of its current mirror ratio. Since the FBC DRAM having a superior affinity with logic LSI process is also shown to have its macro size smaller than the conventional 1T-1C DRAM, the FBC is a promising candidate for next generation embedded DRAM cells.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2005 Custom Integrated Circuits Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages259-262
Number of pages4
ISBN (Print)0780390237, 9780780390232
DOIs
Publication statusPublished - 2005
Externally publishedYes
EventIEEE 2005 Custom Integrated Circuits Conference - San Jose, CA, United States
Duration: 2005 Sep 182005 Sep 21

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2005
ISSN (Print)0886-5930

Other

OtherIEEE 2005 Custom Integrated Circuits Conference
Country/TerritoryUnited States
CitySan Jose, CA
Period05/9/1805/9/21

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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