A 35 ns 16K NMOS Static RAM

Kenji Anami, Masahiko Yoshimoto, Hirofumi Shinohara, Yoshihiro Hirata, Hiroshi Harada, Takao Nakano

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

An NMOS 16K × 1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 μm gate length transistor, high speed sense amplifier, and reduction of delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.

Original languageEnglish
Pages (from-to)815-820
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume17
Issue number5
DOIs
Publication statusPublished - 1982 Oct
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Anami, K., Yoshimoto, M., Shinohara, H., Hirata, Y., Harada, H., & Nakano, T. (1982). A 35 ns 16K NMOS Static RAM. IEEE Journal of Solid-State Circuits, 17(5), 815-820. https://doi.org/10.1109/JSSC.1982.1051824