An NMOS 16K × 1 bit fully static MOS RAM with 35 ns access time has been successfully developed. High speed access time was achieved by the combination of an NMOS process with the 2.2 μm gate length transistor, high speed sense amplifier, and reduction of delay time at the crossunder. The improvements of row and column decoder circuits result in the low active and standby power dissipation of 275 mW and 22.5 mW, respectively. The soft error rate of poly load cell was minimized by reducing the collection efficiency of alpha-particle induced electrons.
ASJC Scopus subject areas
- Electrical and Electronic Engineering