A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology

Torn Nakura; Kimio Ueda; Kazuo Kubo; Yoshio Matsuda; Koichiro Mashiko; Tsutomu Yoshihara

doi:10.1109/4.841503

A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology

Torn Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

This paper describes a 16:1 multiplexer using 0.18 μm SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers.

Original language	English
Pages (from-to)	751-756
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	35
Issue number	5
DOIs	https://doi.org/10.1109/4.841503
Publication status	Published - 2000
Externally published	Yes

Keywords

Multiplexer (mux)
PECL
Phase shift
Pipeline
Selector
SOI

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/4.841503

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@article{2db7f15cfc1b4e8ba33164f7d7cd521b,

title = "A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology",

abstract = "This paper describes a 16:1 multiplexer using 0.18 μm SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers.",

keywords = "Multiplexer (mux), PECL, Phase shift, Pipeline, Selector, SOI",

author = "Torn Nakura and Kimio Ueda and Kazuo Kubo and Yoshio Matsuda and Koichiro Mashiko and Tsutomu Yoshihara",

year = "2000",

doi = "10.1109/4.841503",

language = "English",

volume = "35",

pages = "751--756",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - A 3.6-Gb/s 340-mW 16

T2 - 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology

AU - Nakura, Torn

AU - Ueda, Kimio

AU - Kubo, Kazuo

AU - Matsuda, Yoshio

AU - Mashiko, Koichiro

AU - Yoshihara, Tsutomu

PY - 2000

Y1 - 2000

N2 - This paper describes a 16:1 multiplexer using 0.18 μm SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers.

AB - This paper describes a 16:1 multiplexer using 0.18 μm SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers.

KW - Multiplexer (mux)

KW - PECL

KW - Phase shift

KW - Pipeline

KW - Selector

KW - SOI

UR - http://www.scopus.com/inward/record.url?scp=4344612460&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=4344612460&partnerID=8YFLogxK

U2 - 10.1109/4.841503

DO - 10.1109/4.841503

M3 - Article

AN - SCOPUS:4344612460

VL - 35

SP - 751

EP - 756

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 5

ER -

A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology

Abstract

Keywords

ASJC Scopus subject areas

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