A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology

Torn Nakura; Kimio Ueda; Kazuo Kubo; Yoshio Matsuda; Koichiro Mashiko; Tsutomu Yoshihara

doi:10.1109/4.841503

A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology

Torn Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara

Research output: Contribution to journal › Article

9 Citations (Scopus)

Abstract

This paper describes a 16:1 multiplexer using 0.18 μm SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers.

Original language	English
Pages (from-to)	751-756
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	35
Issue number	5
DOIs	https://doi.org/10.1109/4.841503
Publication status	Published - 2000
Externally published	Yes

Keywords

Multiplexer (mux)
PECL
Phase shift
Pipeline
Selector
SOI

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/4.841503

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Nakura, T., Ueda, K., Kubo, K., Matsuda, Y., Mashiko, K., & Yoshihara, T. (2000). A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. IEEE Journal of Solid-State Circuits, 35(5), 751-756. https://doi.org/10.1109/4.841503

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