Abstract
This paper describes a 16:1 multiplexer using 0.18 μm SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers.
Original language | English |
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Pages (from-to) | 751-756 |
Number of pages | 6 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 35 |
Issue number | 5 |
DOIs | |
Publication status | Published - 2000 |
Externally published | Yes |
Keywords
- Multiplexer (mux)
- PECL
- Phase shift
- Pipeline
- Selector
- SOI
ASJC Scopus subject areas
- Electrical and Electronic Engineering