A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology

Torn Nakura*, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

10 Citations (Scopus)

Abstract

This paper describes a 16:1 multiplexer using 0.18 μm SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers.

Original languageEnglish
Pages (from-to)751-756
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume35
Issue number5
DOIs
Publication statusPublished - 2000
Externally publishedYes

Keywords

  • Multiplexer (mux)
  • PECL
  • Phase shift
  • Pipeline
  • Selector
  • SOI

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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