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A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology
Torn Nakura*, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara
*Corresponding author for this work
Research output: Contribution to journal › Article › peer-review
10
Citations
(Scopus)