A 360Mbin/s CABAC decoder for H.264/AVC level 5.1 applications

Yu Hong, Peilin Liu, Hang Zhang, Zongyuan You, Dajiang Zhou, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    5 Citations (Scopus)

    Abstract

    This paper presents a VLSI architecture of CABAC decoder for H.264/AVC Level 5.1 applications. It adopts a symbol-prediction-based decision engine with extra-bypass decoding support, a four-stage bypass engine, along with dedicated arithmetic decoding modes to increase the throughput rate. It also reduces the context model access time significantly by applying Context Pre-fetch Register Set. The proposed design can decode an average of 1.08 bins per cycle, and can be operated at a maximum frequency of 333MHz using SMIC 0.13μm technology. Therefore, it is able to provide a throughput of 360Mbins/s, and hence can meet the requirements of Level 5.1 in H.264/AVC standard.

    Original languageEnglish
    Title of host publication2009 International SoC Design Conference, ISOCC 2009
    Pages71-74
    Number of pages4
    DOIs
    Publication statusPublished - 2009
    Event2009 International SoC Design Conference, ISOCC 2009 - Busan
    Duration: 2009 Nov 222009 Nov 24

    Other

    Other2009 International SoC Design Conference, ISOCC 2009
    CityBusan
    Period09/11/2209/11/24

    Keywords

    • CABAC
    • H.264
    • Level 5.1

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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