A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode

Yasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Ionue, Masaki Kumanoya, Yoichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

A 4-Mb DRAM that has 38-ns RAS (row-address-strobe) access time and a battery-backup (BBU) mode, and retains data with a 44-μA current requirement is described. The BBU mode is a self-refresh mode. Its power dissipation, however, is reduced in comparison with that of a normal refresh operation. The memory can operate as a standard 4-Mb DRAM, without any timing constraint on CAS (column-address-strobe) and RAS, if the operating cycle does not exceed 16 ms. This approach promises more stable supply at lower cost than specially provided counterparts such as pseudo-SRAMs.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
PublisherPubl by IEEE
Pages230-231, 30
Publication statusPublished - 1990 Jul
Externally publishedYes
Event1990 IEEE International Solid-State Circuits Conference - 37th ISSCC - San Francisco, CA, USA
Duration: 1990 Feb 141990 Feb 16

Other

Other1990 IEEE International Solid-State Circuits Conference - 37th ISSCC
CitySan Francisco, CA, USA
Period90/2/1490/2/16

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Konishi, Y., Dosaka, K., Komatsu, T., Ionue, Y., Kumanoya, M., Tobita, Y., Genjyo, H., Nagatomo, M., & Yoshihara, T. (1990). A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 230-231, 30). Publ by IEEE.