A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode

Yasuhiro Konishi; Katsumi Dosaka; Takahiro Komatsu; Yoshinori Ionue; Masaki Kumanoya; Yoichi Tobita; Hideki Genjyo; Masao Nagatomo; Tsutomu Yoshihara

A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode

Yasuhiro Konishi^*, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Ionue, Masaki Kumanoya, Yoichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

A 4-Mb DRAM that has 38-ns RAS (row-address-strobe) access time and a battery-backup (BBU) mode, and retains data with a 44-μA current requirement is described. The BBU mode is a self-refresh mode. Its power dissipation, however, is reduced in comparison with that of a normal refresh operation. The memory can operate as a standard 4-Mb DRAM, without any timing constraint on CAS (column-address-strobe) and RAS, if the operating cycle does not exceed 16 ms. This approach promises more stable supply at lower cost than specially provided counterparts such as pseudo-SRAMs.

Original language	English
Title of host publication	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Publisher	Publ by IEEE
Pages	230-231, 30
Publication status	Published - 1990 Jul
Externally published	Yes
Event	1990 IEEE International Solid-State Circuits Conference - 37th ISSCC - San Francisco, CA, USA Duration: 1990 Feb 14 → 1990 Feb 16

Other

Other	1990 IEEE International Solid-State Circuits Conference - 37th ISSCC
City	San Francisco, CA, USA
Period	90/2/14 → 90/2/16

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

Konishi, Y, Dosaka, K, Komatsu, T, Ionue, Y, Kumanoya, M, Tobita, Y, Genjyo, H, Nagatomo, M & Yoshihara, T 1990, A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Publ by IEEE, pp. 230-231, 30, 1990 IEEE International Solid-State Circuits Conference - 37th ISSCC, San Francisco, CA, USA, 90/2/14.

@inproceedings{56c743070f9144029718fc3c03039f1b,

title = "A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode",

abstract = "A 4-Mb DRAM that has 38-ns RAS (row-address-strobe) access time and a battery-backup (BBU) mode, and retains data with a 44-μA current requirement is described. The BBU mode is a self-refresh mode. Its power dissipation, however, is reduced in comparison with that of a normal refresh operation. The memory can operate as a standard 4-Mb DRAM, without any timing constraint on CAS (column-address-strobe) and RAS, if the operating cycle does not exceed 16 ms. This approach promises more stable supply at lower cost than specially provided counterparts such as pseudo-SRAMs.",

author = "Yasuhiro Konishi and Katsumi Dosaka and Takahiro Komatsu and Yoshinori Ionue and Masaki Kumanoya and Yoichi Tobita and Hideki Genjyo and Masao Nagatomo and Tsutomu Yoshihara",

year = "1990",

month = jul,

language = "English",

pages = "230--231, 30",

booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Publ by IEEE",

note = "1990 IEEE International Solid-State Circuits Conference - 37th ISSCC ; Conference date: 14-02-1990 Through 16-02-1990",

}

TY - GEN

T1 - A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode

AU - Konishi, Yasuhiro

AU - Dosaka, Katsumi

AU - Komatsu, Takahiro

AU - Ionue, Yoshinori

AU - Kumanoya, Masaki

AU - Tobita, Yoichi

AU - Genjyo, Hideki

AU - Nagatomo, Masao

AU - Yoshihara, Tsutomu

PY - 1990/7

Y1 - 1990/7

N2 - A 4-Mb DRAM that has 38-ns RAS (row-address-strobe) access time and a battery-backup (BBU) mode, and retains data with a 44-μA current requirement is described. The BBU mode is a self-refresh mode. Its power dissipation, however, is reduced in comparison with that of a normal refresh operation. The memory can operate as a standard 4-Mb DRAM, without any timing constraint on CAS (column-address-strobe) and RAS, if the operating cycle does not exceed 16 ms. This approach promises more stable supply at lower cost than specially provided counterparts such as pseudo-SRAMs.

AB - A 4-Mb DRAM that has 38-ns RAS (row-address-strobe) access time and a battery-backup (BBU) mode, and retains data with a 44-μA current requirement is described. The BBU mode is a self-refresh mode. Its power dissipation, however, is reduced in comparison with that of a normal refresh operation. The memory can operate as a standard 4-Mb DRAM, without any timing constraint on CAS (column-address-strobe) and RAS, if the operating cycle does not exceed 16 ms. This approach promises more stable supply at lower cost than specially provided counterparts such as pseudo-SRAMs.

UR - http://www.scopus.com/inward/record.url?scp=0025450663&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025450663&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0025450663

SP - 230-231, 30

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

PB - Publ by IEEE

T2 - 1990 IEEE International Solid-State Circuits Conference - 37th ISSCC

Y2 - 14 February 1990 through 16 February 1990

ER -

A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode

Abstract

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ASJC Scopus subject areas

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