A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode

Yasuhiro Konishi; Katsumi Dosaka; Takahiro Komatsu; Yoshinori Ionue; Masaki Kumanoya; Yoichi Tobita; Hideki Genjyo; Masao Nagatomo; Tsutomu Yoshihara

A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode

Yasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Ionue, Masaki Kumanoya, Yoichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

A 4-Mb DRAM that has 38-ns RAS (row-address-strobe) access time and a battery-backup (BBU) mode, and retains data with a 44-μA current requirement is described. The BBU mode is a self-refresh mode. Its power dissipation, however, is reduced in comparison with that of a normal refresh operation. The memory can operate as a standard 4-Mb DRAM, without any timing constraint on CAS (column-address-strobe) and RAS, if the operating cycle does not exceed 16 ms. This approach promises more stable supply at lower cost than specially provided counterparts such as pseudo-SRAMs.

Original language	English
Title of host publication	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Publisher	Publ by IEEE
Pages	230-231, 30
Publication status	Published - 1990 Jul
Externally published	Yes
Event	1990 IEEE International Solid-State Circuits Conference - 37th ISSCC - San Francisco, CA, USA Duration: 1990 Feb 14 → 1990 Feb 16

Other

Other	1990 IEEE International Solid-State Circuits Conference - 37th ISSCC
City	San Francisco, CA, USA
Period	90/2/14 → 90/2/16

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode. / Konishi, Yasuhiro; Dosaka, Katsumi; Komatsu, Takahiro; Ionue, Yoshinori; Kumanoya, Masaki; Tobita, Yoichi; Genjyo, Hideki; Nagatomo, Masao; Yoshihara, Tsutomu.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Publ by IEEE, 1990. p. 230-231, 30.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Konishi, Y, Dosaka, K, Komatsu, T, Ionue, Y, Kumanoya, M, Tobita, Y, Genjyo, H, Nagatomo, M & Yoshihara, T 1990, A 38 ns 4 Mb DRAM with a battery back-up (BBU) mode. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Publ by IEEE, pp. 230-231, 30, 1990 IEEE International Solid-State Circuits Conference - 37th ISSCC, San Francisco, CA, USA, 90/2/14.

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abstract = "A 4-Mb DRAM that has 38-ns RAS (row-address-strobe) access time and a battery-backup (BBU) mode, and retains data with a 44-μA current requirement is described. The BBU mode is a self-refresh mode. Its power dissipation, however, is reduced in comparison with that of a normal refresh operation. The memory can operate as a standard 4-Mb DRAM, without any timing constraint on CAS (column-address-strobe) and RAS, if the operating cycle does not exceed 16 ms. This approach promises more stable supply at lower cost than specially provided counterparts such as pseudo-SRAMs.",

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AU - Tobita, Yoichi

AU - Genjyo, Hideki

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