A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

Yasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 μA is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4 × 32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode.

Original languageEnglish
Pages (from-to)1112-1117
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume25
Issue number5
DOIs
Publication statusPublished - 1990 Oct
Externally publishedYes

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Dynamic random access storage
Electric power utilization
Data storage equipment
Networks (circuits)
Metals

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Konishi, Y., Dosaka, K., Komatsu, T., Inoue, Y., Kumanoya, M., Tobita, Y., ... Yoshihara, T. (1990). A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode. IEEE Journal of Solid-State Circuits, 25(5), 1112-1117. https://doi.org/10.1109/4.62131

A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode. / Konishi, Yasuhiro; Dosaka, Katsumi; Komatsu, Takahiro; Inoue, Yoshinori; Kumanoya, Masaki; Tobita, Youichi; Genjyo, Hideki; Nagatomo, Masao; Yoshihara, Tsutomu.

In: IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, 10.1990, p. 1112-1117.

Research output: Contribution to journalArticle

Konishi, Y, Dosaka, K, Komatsu, T, Inoue, Y, Kumanoya, M, Tobita, Y, Genjyo, H, Nagatomo, M & Yoshihara, T 1990, 'A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode', IEEE Journal of Solid-State Circuits, vol. 25, no. 5, pp. 1112-1117. https://doi.org/10.1109/4.62131
Konishi Y, Dosaka K, Komatsu T, Inoue Y, Kumanoya M, Tobita Y et al. A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode. IEEE Journal of Solid-State Circuits. 1990 Oct;25(5):1112-1117. https://doi.org/10.1109/4.62131
Konishi, Yasuhiro ; Dosaka, Katsumi ; Komatsu, Takahiro ; Inoue, Yoshinori ; Kumanoya, Masaki ; Tobita, Youichi ; Genjyo, Hideki ; Nagatomo, Masao ; Yoshihara, Tsutomu. / A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode. In: IEEE Journal of Solid-State Circuits. 1990 ; Vol. 25, No. 5. pp. 1112-1117.
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