A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure

S. Yoshimoto, S. Miyano, M. Takamiya, Hirofumi Shinohara, H. Kawaguchi, M. Yoshimoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents a 40-nm 8T SRAM in which bitlines are partially discharged by a selective source line control (SSLC) for low-power operation. The proposed SSLC scheme reduces a read bitline voltage swing in an unselected column with a floating source line (SL) of dedicated read ports. The SL is controlled by an additional NMOS switch that is turned on in a selected column, but the switch is kept off in the remaining unselected columns. The proposed scheme is effective for power reduction in successive address readouts through a single column. Furthermore, this paper introduces an address preset structure. The preset address enables the SRAM to be read out with no access time penalty for preferred use of the SSLC scheme. We fabricated a 16-Kb 8T SRAM test chip in a 40-nm CMOS process and observed that the proposed SSLC scheme with the address preset structure saves 38.1% of the readout power on average.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781467361460
DOIs
Publication statusPublished - 2013 Nov 7
Externally publishedYes
Event35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 - San Jose, CA, United States
Duration: 2013 Sep 222013 Sep 25

Other

Other35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013
CountryUnited States
CitySan Jose, CA
Period13/9/2213/9/25

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Static random access storage
Switches
Electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Yoshimoto, S., Miyano, S., Takamiya, M., Shinohara, H., Kawaguchi, H., & Yoshimoto, M. (2013). A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. In Proceedings of the Custom Integrated Circuits Conference [6658537] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2013.6658537

A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. / Yoshimoto, S.; Miyano, S.; Takamiya, M.; Shinohara, Hirofumi; Kawaguchi, H.; Yoshimoto, M.

Proceedings of the Custom Integrated Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2013. 6658537.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yoshimoto, S, Miyano, S, Takamiya, M, Shinohara, H, Kawaguchi, H & Yoshimoto, M 2013, A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. in Proceedings of the Custom Integrated Circuits Conference., 6658537, Institute of Electrical and Electronics Engineers Inc., 35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013, San Jose, CA, United States, 13/9/22. https://doi.org/10.1109/CICC.2013.6658537
Yoshimoto S, Miyano S, Takamiya M, Shinohara H, Kawaguchi H, Yoshimoto M. A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. In Proceedings of the Custom Integrated Circuits Conference. Institute of Electrical and Electronics Engineers Inc. 2013. 6658537 https://doi.org/10.1109/CICC.2013.6658537
Yoshimoto, S. ; Miyano, S. ; Takamiya, M. ; Shinohara, Hirofumi ; Kawaguchi, H. ; Yoshimoto, M. / A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. Proceedings of the Custom Integrated Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2013.
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