A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption

Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    24 Citations (Scopus)

    Abstract

    A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS.

    Original languageEnglish
    Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
    DOIs
    Publication statusPublished - 2007
    Event54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA
    Duration: 2007 Feb 112007 Feb 15

    Other

    Other54th IEEE International Solid-State Circuits Conference, ISSCC 2007
    CitySan Francisco, CA
    Period07/2/1107/2/15

    Fingerprint

    Clocks
    Electric power utilization
    Processing
    System-on-chip

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture

    Cite this

    Yoshida, Y., Kamei, T., Hayase, K., Shibahara, S., Nishii, O., Hattori, T., ... Kasahara, H. (2007). A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference [4242284] https://doi.org/10.1109/ISSCC.2007.373607

    A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption. / Yoshida, Yutaka; Kamei, Tatsuya; Hayase, Kiyoshi; Shibahara, Shinichi; Nishii, Osamu; Hattori, Toshihiro; Hasegawa, Atsushi; Takada, Masashi; Irie, Naohiko; Uchiyama, Kunio; Odaka, Toshihiko; Takada, Kiwamu; Kimura, Keiji; Kasahara, Hironori.

    Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2007. 4242284.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Yoshida, Y, Kamei, T, Hayase, K, Shibahara, S, Nishii, O, Hattori, T, Hasegawa, A, Takada, M, Irie, N, Uchiyama, K, Odaka, T, Takada, K, Kimura, K & Kasahara, H 2007, A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference., 4242284, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, CA, 07/2/11. https://doi.org/10.1109/ISSCC.2007.373607
    Yoshida Y, Kamei T, Hayase K, Shibahara S, Nishii O, Hattori T et al. A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2007. 4242284 https://doi.org/10.1109/ISSCC.2007.373607
    Yoshida, Yutaka ; Kamei, Tatsuya ; Hayase, Kiyoshi ; Shibahara, Shinichi ; Nishii, Osamu ; Hattori, Toshihiro ; Hasegawa, Atsushi ; Takada, Masashi ; Irie, Naohiko ; Uchiyama, Kunio ; Odaka, Toshihiko ; Takada, Kiwamu ; Kimura, Keiji ; Kasahara, Hironori. / A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2007.
    @inproceedings{f4e3e05ff90e4dc48a10fe0264cd1f3f,
    title = "A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption",
    abstract = "A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS.",
    author = "Yutaka Yoshida and Tatsuya Kamei and Kiyoshi Hayase and Shinichi Shibahara and Osamu Nishii and Toshihiro Hattori and Atsushi Hasegawa and Masashi Takada and Naohiko Irie and Kunio Uchiyama and Toshihiko Odaka and Kiwamu Takada and Keiji Kimura and Hironori Kasahara",
    year = "2007",
    doi = "10.1109/ISSCC.2007.373607",
    language = "English",
    isbn = "1424408539",
    booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

    }

    TY - GEN

    T1 - A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption

    AU - Yoshida, Yutaka

    AU - Kamei, Tatsuya

    AU - Hayase, Kiyoshi

    AU - Shibahara, Shinichi

    AU - Nishii, Osamu

    AU - Hattori, Toshihiro

    AU - Hasegawa, Atsushi

    AU - Takada, Masashi

    AU - Irie, Naohiko

    AU - Uchiyama, Kunio

    AU - Odaka, Toshihiko

    AU - Takada, Kiwamu

    AU - Kimura, Keiji

    AU - Kasahara, Hironori

    PY - 2007

    Y1 - 2007

    N2 - A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS.

    AB - A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS.

    UR - http://www.scopus.com/inward/record.url?scp=34548855675&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=34548855675&partnerID=8YFLogxK

    U2 - 10.1109/ISSCC.2007.373607

    DO - 10.1109/ISSCC.2007.373607

    M3 - Conference contribution

    SN - 1424408539

    SN - 9781424408535

    BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

    ER -