A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption

Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    24 Citations (Scopus)

    Abstract

    A 4320MIPS four-core SoC that supports both SMP and AMP for embedded applications is designed in 90nm CMOS. Each processor-core can be operated with a different frequency dynamically including clock stop, while keeping data cache coherency, to maintain maximum processing performance and to reduce average operating power. The 97.6mm2 die achieves a floating-point performance of 16.8GFLOPS.

    Original languageEnglish
    Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
    DOIs
    Publication statusPublished - 2007
    Event54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA
    Duration: 2007 Feb 112007 Feb 15

    Other

    Other54th IEEE International Solid-State Circuits Conference, ISSCC 2007
    CitySan Francisco, CA
    Period07/2/1107/2/15

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    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture

    Cite this

    Yoshida, Y., Kamei, T., Hayase, K., Shibahara, S., Nishii, O., Hattori, T., Hasegawa, A., Takada, M., Irie, N., Uchiyama, K., Odaka, T., Takada, K., Kimura, K., & Kasahara, H. (2007). A 4320MIPS four-processor core SMP/AMP with individually managed clock frequency for low power consumption. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference [4242284] https://doi.org/10.1109/ISSCC.2007.373607