A 44.3% Peak PAE 25-GHz Stacked-FET Linear Power Amplifier IC with A Varactor-Based Novel Adaptive Load Circuit in 45 nm CMOS SOI

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a 25-GHz-band 4-stacked-FET highly linear high efficiency power amplifier IC in 45-nm CMOS SOI. A novel load circuit which is adaptively controlled by a bias circuit is proposed to achieve high back-off efficiency. A 4-stacked-FET is utilized to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The power amplifier IC is designed, fabricated, and fully evaluated on-wafer. At a supply voltage of 4.5 V, the power amplifier IC has exhibited an output power of 21.1 dBm with a PAE as high as 42.5% at the 1-dB gain compression point (P1dB). In addition, a saturated output power of 22.7 dBm and a peak PAE of 44.3% are obtained. The measured PAEs at 3-dB and 6-dB back-off from P1dB are 35.1% and 21.6%, respectively.

Original languageEnglish
Title of host publication2021 IEEE Asia-Pacific Microwave Conference, APMC 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages181-183
Number of pages3
ISBN (Electronic)9781665437820
DOIs
Publication statusPublished - 2021
Event2021 IEEE Asia-Pacific Microwave Conference, APMC 2021 - Virtual, Online, Australia
Duration: 2021 Nov 282021 Dec 1

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC
Volume2021-November

Conference

Conference2021 IEEE Asia-Pacific Microwave Conference, APMC 2021
Country/TerritoryAustralia
CityVirtual, Online
Period21/11/2821/12/1

Keywords

  • Adaptive bias
  • Adaptive load
  • CMOS SOI
  • High back-off efficiency
  • Power amplifier
  • Stacked-FET

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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