A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues

Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu

Research output: Contribution to journalArticle

24 Citations (Scopus)

Abstract

We propose a new -port SRAM with a single read bit line (SRBL) eight transistors (8T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (Vt) random variations. A Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (RAV) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A Read End detecting Replica circuit (RER) and a Local read bit line Dummy Capacitance (LDC) are introduced to solve this issue. A 128 bit lines - 512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology [1]. The memory cell size is 0.597 μm3, This 2-port SRAM macro achieves 7 times faster access time without misreading.

Original languageEnglish
Pages (from-to)938-943
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume43
Issue number4
DOIs
Publication statusPublished - 2008 Jan
Externally publishedYes

Fingerprint

Static random access storage
Macros
Data storage equipment
Threshold voltage
Transistors
Capacitance
Fabrication
Networks (circuits)

Keywords

  • 2-port SRAM
  • 8T cell
  • Hierarchical bit line
  • Misread
  • Simultaneous read/ write access
  • Single bit line

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues. / Ishikura, Satoshi; Kurumada, Marefusa; Terano, Toshio; Yamagami, Yoshinobu; Kotani, Naoki; Satomi, Katsuji; Nii, Koji; Yabuuchi, Makoto; Tsukamoto, Yasumasa; Ohbayashi, Shigeki; Oashi, Toshiyuki; Makino, Hiroshi; Shinohara, Hirofumi; Akamatsu, Hironori.

In: IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, 01.2008, p. 938-943.

Research output: Contribution to journalArticle

Ishikura, S, Kurumada, M, Terano, T, Yamagami, Y, Kotani, N, Satomi, K, Nii, K, Yabuuchi, M, Tsukamoto, Y, Ohbayashi, S, Oashi, T, Makino, H, Shinohara, H & Akamatsu, H 2008, 'A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues', IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 938-943. https://doi.org/10.1109/JSSC.2008.917568
Ishikura, Satoshi ; Kurumada, Marefusa ; Terano, Toshio ; Yamagami, Yoshinobu ; Kotani, Naoki ; Satomi, Katsuji ; Nii, Koji ; Yabuuchi, Makoto ; Tsukamoto, Yasumasa ; Ohbayashi, Shigeki ; Oashi, Toshiyuki ; Makino, Hiroshi ; Shinohara, Hirofumi ; Akamatsu, Hironori. / A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues. In: IEEE Journal of Solid-State Circuits. 2008 ; Vol. 43, No. 4. pp. 938-943.
@article{e7188413fed94ccd910ae1530bbfa20c,
title = "A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues",
abstract = "We propose a new -port SRAM with a single read bit line (SRBL) eight transistors (8T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (Vt) random variations. A Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (RAV) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A Read End detecting Replica circuit (RER) and a Local read bit line Dummy Capacitance (LDC) are introduced to solve this issue. A 128 bit lines - 512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology [1]. The memory cell size is 0.597 μm3, This 2-port SRAM macro achieves 7 times faster access time without misreading.",
keywords = "2-port SRAM, 8T cell, Hierarchical bit line, Misread, Simultaneous read/ write access, Single bit line",
author = "Satoshi Ishikura and Marefusa Kurumada and Toshio Terano and Yoshinobu Yamagami and Naoki Kotani and Katsuji Satomi and Koji Nii and Makoto Yabuuchi and Yasumasa Tsukamoto and Shigeki Ohbayashi and Toshiyuki Oashi and Hiroshi Makino and Hirofumi Shinohara and Hironori Akamatsu",
year = "2008",
month = "1",
doi = "10.1109/JSSC.2008.917568",
language = "English",
volume = "43",
pages = "938--943",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

TY - JOUR

T1 - A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues

AU - Ishikura, Satoshi

AU - Kurumada, Marefusa

AU - Terano, Toshio

AU - Yamagami, Yoshinobu

AU - Kotani, Naoki

AU - Satomi, Katsuji

AU - Nii, Koji

AU - Yabuuchi, Makoto

AU - Tsukamoto, Yasumasa

AU - Ohbayashi, Shigeki

AU - Oashi, Toshiyuki

AU - Makino, Hiroshi

AU - Shinohara, Hirofumi

AU - Akamatsu, Hironori

PY - 2008/1

Y1 - 2008/1

N2 - We propose a new -port SRAM with a single read bit line (SRBL) eight transistors (8T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (Vt) random variations. A Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (RAV) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A Read End detecting Replica circuit (RER) and a Local read bit line Dummy Capacitance (LDC) are introduced to solve this issue. A 128 bit lines - 512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology [1]. The memory cell size is 0.597 μm3, This 2-port SRAM macro achieves 7 times faster access time without misreading.

AB - We propose a new -port SRAM with a single read bit line (SRBL) eight transistors (8T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (Vt) random variations. A Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (RAV) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A Read End detecting Replica circuit (RER) and a Local read bit line Dummy Capacitance (LDC) are introduced to solve this issue. A 128 bit lines - 512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology [1]. The memory cell size is 0.597 μm3, This 2-port SRAM macro achieves 7 times faster access time without misreading.

KW - 2-port SRAM

KW - 8T cell

KW - Hierarchical bit line

KW - Misread

KW - Simultaneous read/ write access

KW - Single bit line

UR - http://www.scopus.com/inward/record.url?scp=41549166853&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=41549166853&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2008.917568

DO - 10.1109/JSSC.2008.917568

M3 - Article

VL - 43

SP - 938

EP - 943

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 4

ER -