A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues

Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu

Research output: Contribution to journalArticle

27 Citations (Scopus)

Abstract

We propose a new -port SRAM with a single read bit line (SRBL) eight transistors (8T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (Vt) random variations. A Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (RAV) access at the same row by using DBSA with the SRBL-8T cell. A rise of the storage node causes misreading. A Read End detecting Replica circuit (RER) and a Local read bit line Dummy Capacitance (LDC) are introduced to solve this issue. A 128 bit lines - 512 word lines 64 kb 2-port SRAM macro using these schemes was fabricated by a 45 nm bulk CMOS low-standby-power (LSTP) CMOS process technology [1]. The memory cell size is 0.597 μm3, This 2-port SRAM macro achieves 7 times faster access time without misreading.

Original languageEnglish
Pages (from-to)938-943
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume43
Issue number4
DOIs
Publication statusPublished - 2008 Jan 1
Externally publishedYes

Keywords

  • 2-port SRAM
  • 8T cell
  • Hierarchical bit line
  • Misread
  • Simultaneous read/ write access
  • Single bit line

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Ishikura, S., Kurumada, M., Terano, T., Yamagami, Y., Kotani, N., Satomi, K., Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oashi, T., Makino, H., Shinohara, H., & Akamatsu, H. (2008). A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues. IEEE Journal of Solid-State Circuits, 43(4), 938-943. https://doi.org/10.1109/JSSC.2008.917568