A 45-nm 37.3 GOPS/W heterogeneous multi-core SOC with 16/32 bit instruction-set general-purpose core

Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima

    Research output: Contribution to journalArticle

    Abstract

    We built a 12.4mm× 12.4mm, 45-nm CMOS, chip that integrates eight 648-MHz general purpose cores, two matrix processor (MX-2) cores, four flexible engine (FE) cores and media IP (VPU5) to establish heterogeneous multi-core chip architecture. The general purpose core had its IPC (instructions per cycle) performance enhanced by adding 32-bit instructions to the existing 16-bit fixed-length instruction set and executing up to two 32-bit instructions per cycle. Considering these five-toseven years of embedded LSI and increasing trend of access-master within LSI, we predict that the memory usage of single core will not exceed 32-bit physical area (i.e. 4 GB), but chip-total memory usage will exceed 4GB. Based on this prediction, the physical address was expanded from 32-bit to 40-bit. The fabricated chip was tested and a parallel operation of eight general purpose cores and four FE cores and eight data transfer units (DTU) is obtained on AAC (Advanced Audio Coding) encode processing.

    Original languageEnglish
    Pages (from-to)663-669
    Number of pages7
    JournalIEICE Transactions on Electronics
    VolumeE94-C
    Issue number4
    DOIs
    Publication statusPublished - 2011 Apr

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    morpholinoanthracycline MX2

    Keywords

    • Heterogeneous
    • Instruction set
    • MMU

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

    Cite this

    Nishii, O., Yuyama, Y., Ito, M., Kiyoshige, Y., Nitta, Y., Ishikawa, M., ... Maejima, H. (2011). A 45-nm 37.3 GOPS/W heterogeneous multi-core SOC with 16/32 bit instruction-set general-purpose core. IEICE Transactions on Electronics, E94-C(4), 663-669. https://doi.org/10.1587/transele.E94.C.663

    A 45-nm 37.3 GOPS/W heterogeneous multi-core SOC with 16/32 bit instruction-set general-purpose core. / Nishii, Osamu; Yuyama, Yoichi; Ito, Masayuki; Kiyoshige, Yoshikazu; Nitta, Yusuke; Ishikawa, Makoto; Yamada, Tetsuya; Miyakoshi, Junichi; Wada, Yasutaka; Kimura, Keiji; Kasahara, Hironori; Maejima, Hideo.

    In: IEICE Transactions on Electronics, Vol. E94-C, No. 4, 04.2011, p. 663-669.

    Research output: Contribution to journalArticle

    Nishii, O, Yuyama, Y, Ito, M, Kiyoshige, Y, Nitta, Y, Ishikawa, M, Yamada, T, Miyakoshi, J, Wada, Y, Kimura, K, Kasahara, H & Maejima, H 2011, 'A 45-nm 37.3 GOPS/W heterogeneous multi-core SOC with 16/32 bit instruction-set general-purpose core', IEICE Transactions on Electronics, vol. E94-C, no. 4, pp. 663-669. https://doi.org/10.1587/transele.E94.C.663
    Nishii, Osamu ; Yuyama, Yoichi ; Ito, Masayuki ; Kiyoshige, Yoshikazu ; Nitta, Yusuke ; Ishikawa, Makoto ; Yamada, Tetsuya ; Miyakoshi, Junichi ; Wada, Yasutaka ; Kimura, Keiji ; Kasahara, Hironori ; Maejima, Hideo. / A 45-nm 37.3 GOPS/W heterogeneous multi-core SOC with 16/32 bit instruction-set general-purpose core. In: IEICE Transactions on Electronics. 2011 ; Vol. E94-C, No. 4. pp. 663-669.
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