A 45-nm 37.3 GOPS/W heterogeneous multi-core SOC with 16/32 bit instruction-set general-purpose core

Osamu Nishii*, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima

*Corresponding author for this work

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Engineering & Materials Science