A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, H. Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

78 Citations (Scopus)

Abstract

We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage.

Original languageEnglish
Title of host publication2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
Pages202-203
Number of pages2
DOIs
Publication statusPublished - 2008 Sep 23
Event2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC - Honolulu, HI, United States
Duration: 2008 Jun 182008 Jun 20

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
CountryUnited States
CityHonolulu, HI
Period08/6/1808/6/20

Keywords

  • 45nm
  • 6T
  • 8T
  • CMOS
  • DVFS
  • SRAM
  • Stability

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oda, Y., Usui, K., Kawamura, T., Tsuboi, N., Iwasaki, T., Hashimoto, K., Makino, H., & Shinohara, H. (2008). A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. In 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC (pp. 202-203). [4586011] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2008.4586011