A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

75 Citations (Scopus)

Abstract

We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages202-203
Number of pages2
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC - Honolulu, HI, United States
Duration: 2008 Jun 182008 Jun 20

Other

Other2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC
CountryUnited States
CityHonolulu, HI
Period08/6/1808/6/20

Fingerprint

Static random access storage
Electric potential
Macros
Transistors
Voltage scaling
Dynamic frequency scaling

Keywords

  • 45nm
  • 6T
  • 8T
  • CMOS
  • DVFS
  • SRAM
  • Stability

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oda, Y., Usui, K., ... Shinohara, H. (2008). A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 202-203). [4586011] https://doi.org/10.1109/VLSIC.2008.4586011

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. / Nii, K.; Yabuuchi, M.; Tsukamoto, Y.; Ohbayashi, S.; Oda, Y.; Usui, K.; Kawamura, T.; Tsuboi, N.; Iwasaki, T.; Hashimoto, K.; Makino, H.; Shinohara, Hirofumi.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2008. p. 202-203 4586011.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nii, K, Yabuuchi, M, Tsukamoto, Y, Ohbayashi, S, Oda, Y, Usui, K, Kawamura, T, Tsuboi, N, Iwasaki, T, Hashimoto, K, Makino, H & Shinohara, H 2008, A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 4586011, pp. 202-203, 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC, Honolulu, HI, United States, 08/6/18. https://doi.org/10.1109/VLSIC.2008.4586011
Nii K, Yabuuchi M, Tsukamoto Y, Ohbayashi S, Oda Y, Usui K et al. A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2008. p. 202-203. 4586011 https://doi.org/10.1109/VLSIC.2008.4586011
Nii, K. ; Yabuuchi, M. ; Tsukamoto, Y. ; Ohbayashi, S. ; Oda, Y. ; Usui, K. ; Kawamura, T. ; Tsuboi, N. ; Iwasaki, T. ; Hashimoto, K. ; Makino, H. ; Shinohara, Hirofumi. / A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2008. pp. 202-203
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