A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

K. Nii*, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, H. Shinohara

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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