A 45-ns 64-Mb DRAM with a merged match-line test architecture

Shigeru Mori; Hiroshi Miyamoto; Yoshikazu Morooka; Shigeru Kikuda; Makoto Suwa; Mitsuya Kinoshita; Atsushi Hachisuka; Hideaki Arima; Michihiro Yamada; Tsutomu Yoshihara; Shimpei Kayano

doi:10.1109/4.98962

A 45-ns 64-Mb DRAM with a merged match-line test architecture

Shigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

A single 3.3-V 64-Mb dynamic RAM (DRAM) with a chip size of 233.8 mm² has been fabricated using 0.4-μm CMOS technology with double-level metallization. The dual-cell-plate (DCP) cell structure is applied with a cell size of 1.7 μm², and 30-fF cell capacitance has been achieved using an oxynitride layer (t_eff = 5 nm) as the gate insulator. The RAM implements a new data-line architecture called the merged match-line test (MMT) to achieve faster access time and shorter test time with the least chip-area penalty. The MMT architecture makes it possible to get a RAS access time of 45 ns and reduces test time by 1/16000. A parallel MMT technique, which is an extended mode of MMT, leads to the further test-time reduction of 1/64000. Therefore, all 64 Mb are tested in only 1024 cycles, and the test time is only 150 μs with 150-ns cycle time.

Original language	English
Pages (from-to)	1486-1492
Number of pages	7
Journal	IEEE Journal of Solid-State Circuits
Volume	26
Issue number	11
DOIs	https://doi.org/10.1109/4.98962
Publication status	Published - 1991 Nov
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/4.98962

Fingerprint Dive into the research topics of 'A 45-ns 64-Mb DRAM with a merged match-line test architecture'. Together they form a unique fingerprint.

Cite this

A 45-ns 64-Mb DRAM with a merged match-line test architecture. / Mori, Shigeru; Miyamoto, Hiroshi; Morooka, Yoshikazu; Kikuda, Shigeru; Suwa, Makoto; Kinoshita, Mitsuya; Hachisuka, Atsushi; Arima, Hideaki; Yamada, Michihiro; Yoshihara, Tsutomu; Kayano, Shimpei.

In: IEEE Journal of Solid-State Circuits, Vol. 26, No. 11, 11.1991, p. 1486-1492.

Research output: Contribution to journal › Article › peer-review

@article{c5944d8a6cee4449b6507ac2b9b7b92d,

title = "A 45-ns 64-Mb DRAM with a merged match-line test architecture",

abstract = "A single 3.3-V 64-Mb dynamic RAM (DRAM) with a chip size of 233.8 mm2 has been fabricated using 0.4-μm CMOS technology with double-level metallization. The dual-cell-plate (DCP) cell structure is applied with a cell size of 1.7 μm2, and 30-fF cell capacitance has been achieved using an oxynitride layer (teff = 5 nm) as the gate insulator. The RAM implements a new data-line architecture called the merged match-line test (MMT) to achieve faster access time and shorter test time with the least chip-area penalty. The MMT architecture makes it possible to get a RAS access time of 45 ns and reduces test time by 1/16000. A parallel MMT technique, which is an extended mode of MMT, leads to the further test-time reduction of 1/64000. Therefore, all 64 Mb are tested in only 1024 cycles, and the test time is only 150 μs with 150-ns cycle time.",

author = "Shigeru Mori and Hiroshi Miyamoto and Yoshikazu Morooka and Shigeru Kikuda and Makoto Suwa and Mitsuya Kinoshita and Atsushi Hachisuka and Hideaki Arima and Michihiro Yamada and Tsutomu Yoshihara and Shimpei Kayano",

year = "1991",

month = nov,

doi = "10.1109/4.98962",

language = "English",

volume = "26",

pages = "1486--1492",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "11",

}

TY - JOUR

T1 - A 45-ns 64-Mb DRAM with a merged match-line test architecture

AU - Mori, Shigeru

AU - Miyamoto, Hiroshi

AU - Morooka, Yoshikazu

AU - Kikuda, Shigeru

AU - Suwa, Makoto

AU - Kinoshita, Mitsuya

AU - Hachisuka, Atsushi

AU - Arima, Hideaki

AU - Yamada, Michihiro

AU - Yoshihara, Tsutomu

AU - Kayano, Shimpei

PY - 1991/11

Y1 - 1991/11

N2 - A single 3.3-V 64-Mb dynamic RAM (DRAM) with a chip size of 233.8 mm2 has been fabricated using 0.4-μm CMOS technology with double-level metallization. The dual-cell-plate (DCP) cell structure is applied with a cell size of 1.7 μm2, and 30-fF cell capacitance has been achieved using an oxynitride layer (teff = 5 nm) as the gate insulator. The RAM implements a new data-line architecture called the merged match-line test (MMT) to achieve faster access time and shorter test time with the least chip-area penalty. The MMT architecture makes it possible to get a RAS access time of 45 ns and reduces test time by 1/16000. A parallel MMT technique, which is an extended mode of MMT, leads to the further test-time reduction of 1/64000. Therefore, all 64 Mb are tested in only 1024 cycles, and the test time is only 150 μs with 150-ns cycle time.

AB - A single 3.3-V 64-Mb dynamic RAM (DRAM) with a chip size of 233.8 mm2 has been fabricated using 0.4-μm CMOS technology with double-level metallization. The dual-cell-plate (DCP) cell structure is applied with a cell size of 1.7 μm2, and 30-fF cell capacitance has been achieved using an oxynitride layer (teff = 5 nm) as the gate insulator. The RAM implements a new data-line architecture called the merged match-line test (MMT) to achieve faster access time and shorter test time with the least chip-area penalty. The MMT architecture makes it possible to get a RAS access time of 45 ns and reduces test time by 1/16000. A parallel MMT technique, which is an extended mode of MMT, leads to the further test-time reduction of 1/64000. Therefore, all 64 Mb are tested in only 1024 cycles, and the test time is only 150 μs with 150-ns cycle time.

UR - http://www.scopus.com/inward/record.url?scp=0026254979&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026254979&partnerID=8YFLogxK

U2 - 10.1109/4.98962

DO - 10.1109/4.98962

M3 - Article

AN - SCOPUS:0026254979

VL - 26

SP - 1486

EP - 1492

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 11

ER -