A single 3.3-V 64-Mb dynamic RAM (DRAM) with a chip size of 233.8 mm2 has been fabricated using 0.4-μm CMOS technology with double-level metallization. The dual-cell-plate (DCP) cell structure is applied with a cell size of 1.7 μm2, and 30-fF cell capacitance has been achieved using an oxynitride layer (teff = 5 nm) as the gate insulator. The RAM implements a new data-line architecture called the merged match-line test (MMT) to achieve faster access time and shorter test time with the least chip-area penalty. The MMT architecture makes it possible to get a RAS access time of 45 ns and reduces test time by 1/16000. A parallel MMT technique, which is an extended mode of MMT, leads to the further test-time reduction of 1/64000. Therefore, all 64 Mb are tested in only 1024 cycles, and the test time is only 150 μs with 150-ns cycle time.
ASJC Scopus subject areas
- Electrical and Electronic Engineering