A 45-ns 64-Mb DRAM with a merged match-line test architecture

Shigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

A single 3.3-V 64-Mb dynamic RAM (DRAM) with a chip size of 233.8 mm2 has been fabricated using 0.4-μm CMOS technology with double-level metallization. The dual-cell-plate (DCP) cell structure is applied with a cell size of 1.7 μm2, and 30-fF cell capacitance has been achieved using an oxynitride layer (teff = 5 nm) as the gate insulator. The RAM implements a new data-line architecture called the merged match-line test (MMT) to achieve faster access time and shorter test time with the least chip-area penalty. The MMT architecture makes it possible to get a RAS access time of 45 ns and reduces test time by 1/16000. A parallel MMT technique, which is an extended mode of MMT, leads to the further test-time reduction of 1/64000. Therefore, all 64 Mb are tested in only 1024 cycles, and the test time is only 150 μs with 150-ns cycle time.

Original languageEnglish
Pages (from-to)1486-1492
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume26
Issue number11
DOIs
Publication statusPublished - 1991 Nov
Externally publishedYes

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Random access storage
Metallizing
Capacitance

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Mori, S., Miyamoto, H., Morooka, Y., Kikuda, S., Suwa, M., Kinoshita, M., ... Kayano, S. (1991). A 45-ns 64-Mb DRAM with a merged match-line test architecture. IEEE Journal of Solid-State Circuits, 26(11), 1486-1492. https://doi.org/10.1109/4.98962

A 45-ns 64-Mb DRAM with a merged match-line test architecture. / Mori, Shigeru; Miyamoto, Hiroshi; Morooka, Yoshikazu; Kikuda, Shigeru; Suwa, Makoto; Kinoshita, Mitsuya; Hachisuka, Atsushi; Arima, Hideaki; Yamada, Michihiro; Yoshihara, Tsutomu; Kayano, Shimpei.

In: IEEE Journal of Solid-State Circuits, Vol. 26, No. 11, 11.1991, p. 1486-1492.

Research output: Contribution to journalArticle

Mori, S, Miyamoto, H, Morooka, Y, Kikuda, S, Suwa, M, Kinoshita, M, Hachisuka, A, Arima, H, Yamada, M, Yoshihara, T & Kayano, S 1991, 'A 45-ns 64-Mb DRAM with a merged match-line test architecture', IEEE Journal of Solid-State Circuits, vol. 26, no. 11, pp. 1486-1492. https://doi.org/10.1109/4.98962
Mori S, Miyamoto H, Morooka Y, Kikuda S, Suwa M, Kinoshita M et al. A 45-ns 64-Mb DRAM with a merged match-line test architecture. IEEE Journal of Solid-State Circuits. 1991 Nov;26(11):1486-1492. https://doi.org/10.1109/4.98962
Mori, Shigeru ; Miyamoto, Hiroshi ; Morooka, Yoshikazu ; Kikuda, Shigeru ; Suwa, Makoto ; Kinoshita, Mitsuya ; Hachisuka, Atsushi ; Arima, Hideaki ; Yamada, Michihiro ; Yoshihara, Tsutomu ; Kayano, Shimpei. / A 45-ns 64-Mb DRAM with a merged match-line test architecture. In: IEEE Journal of Solid-State Circuits. 1991 ; Vol. 26, No. 11. pp. 1486-1492.
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