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A 45-ns 64-Mb DRAM with a merged match-line test architecture
Shigeru Mori*, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano
*Corresponding author for this work
Research output: Contribution to journal › Article › peer-review
9
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(Scopus)