A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist

M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi, Y. Nakase, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

55 Citations (Scopus)

Abstract

We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. A negative bias technique for VSS and bitline (BL) enables us to achieve not only low power and high access speed, but also the large cell stability and write ability. Using 45-nm CMOS technology, we fabricated the SRAM macro based on our proposal and confirmed that the 1Mbit-SRAM successfully operated at 0.6V. The active power is reduced by 66%, compared to the conventional 6T-SRAM.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages158-159
Number of pages2
Publication statusPublished - 2009
Externally publishedYes
Event2009 Symposium on VLSI Circuits - Kyoto, Japan
Duration: 2009 Jun 162009 Jun 18

Other

Other2009 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period09/6/1609/6/18

Fingerprint

Static random access storage
Macros
Electric potential

Keywords

  • 45nm
  • 8T
  • Assist circuit
  • Cross point
  • DVFS
  • SRAM

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Yabuuchi, M., Nii, K., Tsukamoto, Y., Ohbayashi, S., Nakase, Y., & Shinohara, H. (2009). A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 158-159). [5205389]

A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist. / Yabuuchi, M.; Nii, K.; Tsukamoto, Y.; Ohbayashi, S.; Nakase, Y.; Shinohara, Hirofumi.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2009. p. 158-159 5205389.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yabuuchi, M, Nii, K, Tsukamoto, Y, Ohbayashi, S, Nakase, Y & Shinohara, H 2009, A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 5205389, pp. 158-159, 2009 Symposium on VLSI Circuits, Kyoto, Japan, 09/6/16.
Yabuuchi M, Nii K, Tsukamoto Y, Ohbayashi S, Nakase Y, Shinohara H. A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2009. p. 158-159. 5205389
Yabuuchi, M. ; Nii, K. ; Tsukamoto, Y. ; Ohbayashi, S. ; Nakase, Y. ; Shinohara, Hirofumi. / A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2009. pp. 158-159
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