A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist

M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi, Y. Nakase, H. Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

61 Citations (Scopus)

Abstract

We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. A negative bias technique for VSS and bitline (BL) enables us to achieve not only low power and high access speed, but also the large cell stability and write ability. Using 45-nm CMOS technology, we fabricated the SRAM macro based on our proposal and confirmed that the 1Mbit-SRAM successfully operated at 0.6V. The active power is reduced by 66%, compared to the conventional 6T-SRAM.

Original languageEnglish
Title of host publication2009 Symposium on VLSI Circuits
Pages158-159
Number of pages2
Publication statusPublished - 2009 Nov 18
Externally publishedYes
Event2009 Symposium on VLSI Circuits - Kyoto, Japan
Duration: 2009 Jun 162009 Jun 18

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2009 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period09/6/1609/6/18

Keywords

  • 45nm
  • 8T
  • Assist circuit
  • Cross point
  • DVFS
  • SRAM

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Yabuuchi, M., Nii, K., Tsukamoto, Y., Ohbayashi, S., Nakase, Y., & Shinohara, H. (2009). A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist. In 2009 Symposium on VLSI Circuits (pp. 158-159). [5205389] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).