A 45nm low-standby-power embedded SRAM with improved immunity against process and temperature variations

Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

49 Citations (Scopus)

Abstract

A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided V DD line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245μm 2 and 0.327μm 2 are fabricated. Measurements show that the SNM exceeds 120mV and the write margin improves by 15% in the worst PVT condition.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
Duration: 2007 Feb 112007 Feb 15

Other

Other54th IEEE International Solid-State Circuits Conference, ISSCC 2007
CountryUnited States
CitySan Francisco, CA
Period07/2/1107/2/15

Fingerprint

Static random access storage
Networks (circuits)
Data storage equipment
Temperature

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Yabuuchi, M., Nii, K., Tsukamoto, Y., Ohbayashi, S., Imaoka, S., Makino, H., ... Shinohara, H. (2007). A 45nm low-standby-power embedded SRAM with improved immunity against process and temperature variations. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference [4242397] https://doi.org/10.1109/ISSCC.2007.373426

A 45nm low-standby-power embedded SRAM with improved immunity against process and temperature variations. / Yabuuchi, Makoto; Nii, Koji; Tsukamoto, Yasumasa; Ohbayashi, Shigeki; Imaoka, Susumu; Makino, Hiroshi; Yamagami, Yoshinobu; Ishikura, Satoshi; Terano, Toshio; Oashi, Toshiyuki; Hashimoto, Keiji; Sebe, Akio; Okazaki, Gen; Satomi, Katsuji; Akamatsu, Hironori; Shinohara, Hirofumi.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2007. 4242397.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yabuuchi, M, Nii, K, Tsukamoto, Y, Ohbayashi, S, Imaoka, S, Makino, H, Yamagami, Y, Ishikura, S, Terano, T, Oashi, T, Hashimoto, K, Sebe, A, Okazaki, G, Satomi, K, Akamatsu, H & Shinohara, H 2007, A 45nm low-standby-power embedded SRAM with improved immunity against process and temperature variations. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference., 4242397, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, CA, United States, 07/2/11. https://doi.org/10.1109/ISSCC.2007.373426
Yabuuchi M, Nii K, Tsukamoto Y, Ohbayashi S, Imaoka S, Makino H et al. A 45nm low-standby-power embedded SRAM with improved immunity against process and temperature variations. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2007. 4242397 https://doi.org/10.1109/ISSCC.2007.373426
Yabuuchi, Makoto ; Nii, Koji ; Tsukamoto, Yasumasa ; Ohbayashi, Shigeki ; Imaoka, Susumu ; Makino, Hiroshi ; Yamagami, Yoshinobu ; Ishikura, Satoshi ; Terano, Toshio ; Oashi, Toshiyuki ; Hashimoto, Keiji ; Sebe, Akio ; Okazaki, Gen ; Satomi, Katsuji ; Akamatsu, Hironori ; Shinohara, Hirofumi. / A 45nm low-standby-power embedded SRAM with improved immunity against process and temperature variations. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2007.
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