A 530 Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

Dajiang Zhou, Jinjia Zhou, Xun He, Jiayi Zhu, Ji Kong, Peilin Liu, Satoshi Goto

Research output: Contribution to journalArticle

45 Citations (Scopus)

Abstract

The increased resolution of Quad Full High Definition (QFHD) offers significantly enhanced visual experience. However, the corresponding huge data throughput of up to 530 Mpixels/s greatly challenges the design of real-time video decoder VLSI with the extensive requirement on both DRAM bandwidth and computational power. In this work, a lossless frame recompression technique and a partial MB reordering scheme are proposed to save the DRAM access of a QFHD video decoder chip. Besides, pipelining and parallelization techniques such as NAL/slice-parallel entropy decoding are implemented to efficiently enhance its computational power. The chip supporting H.264/AVC high profile is fabricated in 90 nm CMOS and verified. It delivers a maximum throughput of 4096×2160@60fps, which is at least 4.3 times higher than the state-of-the-art. DRAM bandwidth requirement is reduced by typically 51%, which fits the design into a 64-bit LPDDR SDRAM interface and results in 58% DRAM power saving. Meanwhile, the core energy is saved by 54% by pipelining and parallelization.

Original languageEnglish
Article number5727920
Pages (from-to)777-788
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume46
Issue number4
DOIs
Publication statusPublished - 2011 Apr
Externally publishedYes

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Keywords

  • DRAM bandwidth
  • embedded compression
  • frame recompression
  • H.264/AVC
  • QFHD
  • ultra high definition
  • video decoder

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Zhou, D., Zhou, J., He, X., Zhu, J., Kong, J., Liu, P., & Goto, S. (2011). A 530 Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip. IEEE Journal of Solid-State Circuits, 46(4), 777-788. [5727920]. https://doi.org/10.1109/JSSC.2011.2109550