A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

Dajiang Zhou, Jinjia Zhou, Xun He, Ji Kong, Jiayi Zhu, Peilin Liu, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

An H.264/AVC HP video decoder is implemented in 90nm CMOS. Its maximum throughput reaches 4096×2160@60fps, which is at least 4.3× higher than the state-of-the-art. By using partial MB reordering and lossless frame recompression, 51% of DRAM bandwidth is reduced which results in 58% DRAM power saving. Meanwhile, various efficient parallelization techniques contribute to a core energy saving of 54%.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages171-172
Number of pages2
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI
Duration: 2010 Jun 162010 Jun 18

Other

Other2010 24th Symposium on VLSI Circuits, VLSIC 2010
CityHonolulu, HI
Period10/6/1610/6/18

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Zhou, D., Zhou, J., He, X., Kong, J., Zhu, J., Liu, P., & Goto, S. (2010). A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 171-172). [5560311] https://doi.org/10.1109/VLSIC.2010.5560311