A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

Takeshi Nakayama, Shin ichi Kobayashi, Yoshikazu Miyawaki, Yasushi Terada, Natsuo Ajika, Makoto Ohi, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara, Kimio Suzuki

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks. in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm × 2.0 μm and a chip size of 6.5 mm × 18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process.

Original languageEnglish
Pages (from-to)1600-1605
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume26
Issue number11
DOIs
Publication statusPublished - 1991 Nov
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Nakayama, T., Kobayashi, S. I., Miyawaki, Y., Terada, Y., Ajika, N., Ohi, M., Arima, H., Matsukawa, T., Yoshihara, T., & Suzuki, K. (1991). A 60-ns 16-Mb flash EEPROM with program and erase sequence controller. IEEE Journal of Solid-State Circuits, 26(11), 1600-1605. https://doi.org/10.1109/4.98978