A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

Takeshi Nakayama; Shin ichi Kobayashi; Yoshikazu Miyawaki; Yasushi Terada; Natsuo Ajika; Makoto Ohi; Hideaki Arima; Takayuki Matsukawa; Tsutomu Yoshihara; Kimio Suzuki

doi:10.1109/4.98978

A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

Takeshi Nakayama^*, Shin ichi Kobayashi, Yoshikazu Miyawaki, Yasushi Terada, Natsuo Ajika, Makoto Ohi, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara, Kimio Suzuki

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks. in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm × 2.0 μm and a chip size of 6.5 mm × 18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process.

Original language	English
Pages (from-to)	1600-1605
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	26
Issue number	11
DOIs	https://doi.org/10.1109/4.98978
Publication status	Published - 1991 Nov
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/4.98978

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title = "A 60-ns 16-Mb flash EEPROM with program and erase sequence controller",

abstract = "An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks. in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm × 2.0 μm and a chip size of 6.5 mm × 18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process.",

author = "Takeshi Nakayama and Kobayashi, {Shin ichi} and Yoshikazu Miyawaki and Yasushi Terada and Natsuo Ajika and Makoto Ohi and Hideaki Arima and Takayuki Matsukawa and Tsutomu Yoshihara and Kimio Suzuki",

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AU - Nakayama, Takeshi

AU - Kobayashi, Shin ichi

AU - Miyawaki, Yoshikazu

AU - Terada, Yasushi

AU - Ajika, Natsuo

AU - Ohi, Makoto

AU - Arima, Hideaki

AU - Matsukawa, Takayuki

AU - Yoshihara, Tsutomu

AU - Suzuki, Kimio

PY - 1991/11

Y1 - 1991/11

N2 - An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks. in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm × 2.0 μm and a chip size of 6.5 mm × 18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process.

AB - An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks. in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm × 2.0 μm and a chip size of 6.5 mm × 18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process.

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A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

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