A 60-ns 4-Mbit CMOS DRAM with Built-In Self-Test Function

Takashi Ohsawa, Tohru Furuyama, Yohji Watanabe, Hiroto Tanaka, Kenji Natori, Satoshi Shinozaki, Takeshi Tanaka, Satoshi Yamano, Yohsei Nagahama, Natsuki Kushiyama, Kenji Tsuchida

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Abstract

A 4-Mbit CMOS DRAM measuring 6.9×16.11 mm2 has been fabricated using a 0.9-µm twin-tub CMOS, triple-poly, single-metal process technology. N-channel depletion-type trench cells, 2.5 × 5.5 µm2 each, are incorporated in a p-well. A novel built-in self-test (BIST) function which enables a simultaneous and automatic test of all the memory devices on a board is introduced to reduce the RAM testing time in a system. This function is effective for system maintenance and a daily start-up test even in a relatively small system. A high-speed low-power 4-Mbit CMOS DRAM with 60-ns access time, 50-mA active current, and 200-µA standby current is realized by widening the DQ line bus which connects the sense amplifiers with the DQ buffers, thereby reducing the parasitic capacitance of the DQ lines.

Original languageEnglish
Pages (from-to)663-668
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume22
Issue number5
DOIs
Publication statusPublished - 1987 Oct

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Ohsawa, T., Furuyama, T., Watanabe, Y., Tanaka, H., Natori, K., Shinozaki, S., Tanaka, T., Yamano, S., Nagahama, Y., Kushiyama, N., & Tsuchida, K. (1987). A 60-ns 4-Mbit CMOS DRAM with Built-In Self-Test Function. IEEE Journal of Solid-State Circuits, 22(5), 663-668. https://doi.org/10.1109/JSSC.1987.1052797