A 64-cycle-per-MB joint parameter decoder architecture for ultra high definition H.264/AVC applications

Jinjia Zhou; Dajiang Zhou; Xun He; Satoshi Goto

doi:10.1109/ISPACS.2009.5383903

A 64-cycle-per-MB joint parameter decoder architecture for ultra high definition H.264/AVC applications

Jinjia Zhou^*, Dajiang Zhou, Xun He, Satoshi Goto

^*Corresponding author for this work

Information, Production and Systems Research Center

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. To achieve an efficient design, compact data storage formats are proposed for SRAM size saving and DRAM bandwidth reduction. Moreover, a 64-cycle-per-MB pipeline with simplified control modes is designed to enhance the throughput. Experimental results show the proposed architecture is capable of real-time QFHD@60fps decoding at less than 133MHz, with 26.7k logic gates and 3.6kB SRAM.

Original language	English
Title of host publication	ISPACS 2009 - 2009 International Symposium on Intelligent Signal Processing and Communication Systems, Proceedings
Pages	49-52
Number of pages	4
DOIs	https://doi.org/10.1109/ISPACS.2009.5383903
Publication status	Published - 2009
Event	2009 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2009 - Kanazawa Duration: 2009 Dec 7 → 2009 Dec 9

Other

Other	2009 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2009
City	Kanazawa
Period	09/12/7 → 09/12/9

ASJC Scopus subject areas

Computer Networks and Communications
Signal Processing
Electrical and Electronic Engineering
Communication

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10.1109/ISPACS.2009.5383903

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A 64-cycle-per-MB joint parameter decoder architecture for ultra high definition H.264/AVC applications. / Zhou, Jinjia; Zhou, Dajiang; He, Xun et al.

ISPACS 2009 - 2009 International Symposium on Intelligent Signal Processing and Communication Systems, Proceedings. 2009. p. 49-52 5383903.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhou, J, Zhou, D, He, X & Goto, S 2009, A 64-cycle-per-MB joint parameter decoder architecture for ultra high definition H.264/AVC applications. in ISPACS 2009 - 2009 International Symposium on Intelligent Signal Processing and Communication Systems, Proceedings., 5383903, pp. 49-52, 2009 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2009, Kanazawa, 09/12/7. https://doi.org/10.1109/ISPACS.2009.5383903

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A 64-cycle-per-MB joint parameter decoder architecture for ultra high definition H.264/AVC applications

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