A 64-cycle-per-MB joint parameter decoder architecture for ultra high definition H.264/AVC applications

Jinjia Zhou, Dajiang Zhou, Xun He, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, VLSI architecture of a joint parameter decoder is proposed to realize the calculation of motion vector (MV), intra prediction mode (IPM) and boundary strength (BS) for ultra high definition H.264/AVC applications. To achieve an efficient design, compact data storage formats are proposed for SRAM size saving and DRAM bandwidth reduction. Moreover, a 64-cycle-per-MB pipeline with simplified control modes is designed to enhance the throughput. Experimental results show the proposed architecture is capable of real-time QFHD@60fps decoding at less than 133MHz, with 26.7k logic gates and 3.6kB SRAM.

Original languageEnglish
Title of host publicationISPACS 2009 - 2009 International Symposium on Intelligent Signal Processing and Communication Systems, Proceedings
Pages49-52
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2009 - Kanazawa
Duration: 2009 Dec 72009 Dec 9

Other

Other2009 International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2009
CityKanazawa
Period09/12/709/12/9

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ASJC Scopus subject areas

  • Computer Networks and Communications
  • Signal Processing
  • Electrical and Electronic Engineering
  • Communication

Cite this

Zhou, J., Zhou, D., He, X., & Goto, S. (2009). A 64-cycle-per-MB joint parameter decoder architecture for ultra high definition H.264/AVC applications. In ISPACS 2009 - 2009 International Symposium on Intelligent Signal Processing and Communication Systems, Proceedings (pp. 49-52). [5383903] https://doi.org/10.1109/ISPACS.2009.5383903