A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2%. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 × 36 m2 using 65 nm technology.

Original languageEnglish
Pages (from-to)96-108
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Volume43
Issue number1
DOIs
Publication statusPublished - 2008
Externally publishedYes

Fingerprint

Static random access storage
Electric fuses
Redundancy
Transistors
Trimming
Networks (circuits)
Repair

Keywords

  • 65 nm CMOS
  • 6T-SRAM
  • CMOS
  • embedded SRAM
  • fuse
  • known good die (KGD)
  • redundancy
  • SRAM
  • wafer level burn-in

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. / Ohbayashi, Shigeki; Yabuuchi, Makoto; Kono, Kazushi; Oda, Yuji; Imaoka, Susumu; Usui, Keiichi; Yonezu, Toshiaki; Iwamoto, Takeshi; Nii, Koji; Tsukamoto, Yasumasa; Arakawa, Masashi; Uchida, Takahiro; Okada, Masakazu; Ishii, Atsushi; Yoshihara, Tsutomu; Makino, Hiroshi; Ishibashi, Koichiro; Shinohara, Hirofumi.

In: IEEE Journal of Solid-State Circuits, Vol. 43, No. 1, 2008, p. 96-108.

Research output: Contribution to journalArticle

Ohbayashi, S, Yabuuchi, M, Kono, K, Oda, Y, Imaoka, S, Usui, K, Yonezu, T, Iwamoto, T, Nii, K, Tsukamoto, Y, Arakawa, M, Uchida, T, Okada, M, Ishii, A, Yoshihara, T, Makino, H, Ishibashi, K & Shinohara, H 2008, 'A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die', IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 96-108. https://doi.org/10.1109/JSSC.2007.908004
Ohbayashi, Shigeki ; Yabuuchi, Makoto ; Kono, Kazushi ; Oda, Yuji ; Imaoka, Susumu ; Usui, Keiichi ; Yonezu, Toshiaki ; Iwamoto, Takeshi ; Nii, Koji ; Tsukamoto, Yasumasa ; Arakawa, Masashi ; Uchida, Takahiro ; Okada, Masakazu ; Ishii, Atsushi ; Yoshihara, Tsutomu ; Makino, Hiroshi ; Ishibashi, Koichiro ; Shinohara, Hirofumi. / A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. In: IEEE Journal of Solid-State Circuits. 2008 ; Vol. 43, No. 1. pp. 96-108.
@article{d78947b23a1442ec8360330ac32a175b,
title = "A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die",
abstract = "We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2{\%}. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 × 36 m2 using 65 nm technology.",
keywords = "65 nm CMOS, 6T-SRAM, CMOS, embedded SRAM, fuse, known good die (KGD), redundancy, SRAM, wafer level burn-in",
author = "Shigeki Ohbayashi and Makoto Yabuuchi and Kazushi Kono and Yuji Oda and Susumu Imaoka and Keiichi Usui and Toshiaki Yonezu and Takeshi Iwamoto and Koji Nii and Yasumasa Tsukamoto and Masashi Arakawa and Takahiro Uchida and Masakazu Okada and Atsushi Ishii and Tsutomu Yoshihara and Hiroshi Makino and Koichiro Ishibashi and Hirofumi Shinohara",
year = "2008",
doi = "10.1109/JSSC.2007.908004",
language = "English",
volume = "43",
pages = "96--108",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "1",

}

TY - JOUR

T1 - A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

AU - Ohbayashi, Shigeki

AU - Yabuuchi, Makoto

AU - Kono, Kazushi

AU - Oda, Yuji

AU - Imaoka, Susumu

AU - Usui, Keiichi

AU - Yonezu, Toshiaki

AU - Iwamoto, Takeshi

AU - Nii, Koji

AU - Tsukamoto, Yasumasa

AU - Arakawa, Masashi

AU - Uchida, Takahiro

AU - Okada, Masakazu

AU - Ishii, Atsushi

AU - Yoshihara, Tsutomu

AU - Makino, Hiroshi

AU - Ishibashi, Koichiro

AU - Shinohara, Hirofumi

PY - 2008

Y1 - 2008

N2 - We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2%. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 × 36 m2 using 65 nm technology.

AB - We propose a wafer level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable Cu E-trim fuse repair for an embedded 6T-SRAM to achieve a known good die (KGD) SoC. We fabricated a 16 Mb SRAM with these techniques using 65 nm LSTP technology, and confirmed the efficient operations of these techniques. The WLBI mode enables simultaneous write operation for 6T-SRAM, and has no area penalty and a speed penalty of only 50 ps. The leak-bit redundancy for 6T-SRAM can reduce the infant mortality of the bare die, and improves the standby current distribution. The area penalty is less than 2%. The Cu E-trim fuse can be used beyond the 45 nm advanced process technology. The fuse requires no additional wafer process steps. Using only 1.2 V core transistors will allow CMOS technology scaling to enable fuse circuit size reduction. The trimming transistor is placed under the fuse due to there being no cracking around the trimmed position. We achieve the small fuse circuit size of 6 × 36 m2 using 65 nm technology.

KW - 65 nm CMOS

KW - 6T-SRAM

KW - CMOS

KW - embedded SRAM

KW - fuse

KW - known good die (KGD)

KW - redundancy

KW - SRAM

KW - wafer level burn-in

UR - http://www.scopus.com/inward/record.url?scp=85008019201&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85008019201&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2007.908004

DO - 10.1109/JSSC.2007.908004

M3 - Article

AN - SCOPUS:85008019201

VL - 43

SP - 96

EP - 108

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 1

ER -