A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits

S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, M. Igarashi, M. Takeuchi, H. Kawashima, H. Makino, Y. Yamaguchi, K. Tsukamoto, Masahide Inuishi, K. Ishibashi, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

41 Citations (Scopus)

Abstract

We propose a new design scheme to improve the SRAM read and write operation margins in the presence of a large Vth variability. By applying this scheme to a 0.494 μm 2 SRAM cell with a β ratio of 1, which is an aggressively small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth value using a 65 nm LSTP CMOS technology.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages17-18
Number of pages2
Publication statusPublished - 2006
Externally publishedYes
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: 2006 Jun 152006 Jun 17

Other

Other2006 Symposium on VLSI Circuits, VLSIC
CountryUnited States
CityHonolulu, HI
Period06/6/1506/6/17

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Keywords

  • 65 nm CMOS
  • 6T-SRAM
  • Assist circuit
  • CMOS
  • Variability
  • Vth curve

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Ohbayashi, S., Yabuuchi, M., Nii, K., Tsukamoto, Y., Imaoka, S., Oda, Y., Igarashi, M., Takeuchi, M., Kawashima, H., Makino, H., Yamaguchi, Y., Tsukamoto, K., Inuishi, M., Ishibashi, K., & Shinohara, H. (2006). A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 17-18). [1705290]