A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits

S. Ohbayashi*, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, M. Igarashi, M. Takeuchi, H. Kawashima, H. Makino, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, K. Ishibashi, H. Shinohara

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

43 Citations (Scopus)

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Engineering & Materials Science