A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nil, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

Research output: Contribution to journalArticle

84 Citations (Scopus)

Abstract

In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-μm2 SRAM cell with a β ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.

Original languageEnglish
Pages (from-to)820-829
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume42
Issue number4
DOIs
Publication statusPublished - 2007 Apr
Externally publishedYes

Fingerprint

Static random access storage
Networks (circuits)
System-on-chip

Keywords

  • 65-nm CMOS
  • 6T-SRAM
  • Assist circuit
  • CMOS
  • Embedded SRAM
  • SRAM
  • Vth curve
  • Vth-variability

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits. / Ohbayashi, Shigeki; Yabuuchi, Makoto; Nil, Koji; Tsukamoto, Yasumasa; Imaoka, Susumu; Oda, Yuji; Yoshihara, Tsutomu; Igarashi, Motoshige; Takeuchi, Masahiko; Kawashima, Hiroshi; Yamaguchi, Yasuo; Tsukamoto, Kazuhiro; Inuishi, Masahide; Makino, Hiroshi; Ishibashi, Koichiro; Shinohara, Hirofumi.

In: IEEE Journal of Solid-State Circuits, Vol. 42, No. 4, 04.2007, p. 820-829.

Research output: Contribution to journalArticle

Ohbayashi, S, Yabuuchi, M, Nil, K, Tsukamoto, Y, Imaoka, S, Oda, Y, Yoshihara, T, Igarashi, M, Takeuchi, M, Kawashima, H, Yamaguchi, Y, Tsukamoto, K, Inuishi, M, Makino, H, Ishibashi, K & Shinohara, H 2007, 'A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits', IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 820-829. https://doi.org/10.1109/JSSC.2007.891648
Ohbayashi, Shigeki ; Yabuuchi, Makoto ; Nil, Koji ; Tsukamoto, Yasumasa ; Imaoka, Susumu ; Oda, Yuji ; Yoshihara, Tsutomu ; Igarashi, Motoshige ; Takeuchi, Masahiko ; Kawashima, Hiroshi ; Yamaguchi, Yasuo ; Tsukamoto, Kazuhiro ; Inuishi, Masahide ; Makino, Hiroshi ; Ishibashi, Koichiro ; Shinohara, Hirofumi. / A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits. In: IEEE Journal of Solid-State Circuits. 2007 ; Vol. 42, No. 4. pp. 820-829.
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