A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

Shigeki Ohbayashi; Makoto Yabuuchi; Koji Nil; Yasumasa Tsukamoto; Susumu Imaoka; Yuji Oda; Tsutomu Yoshihara; Motoshige Igarashi; Masahiko Takeuchi; Hiroshi Kawashima; Yasuo Yamaguchi; Kazuhiro Tsukamoto; Masahide Inuishi; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara

doi:10.1109/JSSC.2007.891648

A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

Shigeki Ohbayashi^*, Makoto Yabuuchi, Koji Nil, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

104 Citations (Scopus)

Abstract

In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-μm² SRAM cell with a β ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.

Original language	English
Pages (from-to)	820-829
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	42
Issue number	4
DOIs	https://doi.org/10.1109/JSSC.2007.891648
Publication status	Published - 2007 Apr
Externally published	Yes

Keywords

65-nm CMOS
6T-SRAM
Assist circuit
CMOS
Embedded SRAM
SRAM
Vth curve
Vth-variability

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.2007.891648

Cite this

Ohbayashi, S., Yabuuchi, M., Nil, K., Tsukamoto, Y., Imaoka, S., Oda, Y., Yoshihara, T., Igarashi, M., Takeuchi, M., Kawashima, H., Yamaguchi, Y., Tsukamoto, K., Inuishi, M., Makino, H., Ishibashi, K., & Shinohara, H. (2007). A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits. IEEE Journal of Solid-State Circuits, 42(4), 820-829. https://doi.org/10.1109/JSSC.2007.891648

Ohbayashi, S, Yabuuchi, M, Nil, K, Tsukamoto, Y, Imaoka, S, Oda, Y, Yoshihara, T, Igarashi, M, Takeuchi, M, Kawashima, H, Yamaguchi, Y, Tsukamoto, K, Inuishi, M, Makino, H, Ishibashi, K & Shinohara, H 2007, 'A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits', IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 820-829. https://doi.org/10.1109/JSSC.2007.891648

@article{0090fbbe057247a0833c2cb1f391358d,

title = "A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits",

abstract = "In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-μm2 SRAM cell with a β ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.",

keywords = "65-nm CMOS, 6T-SRAM, Assist circuit, CMOS, Embedded SRAM, SRAM, Vth curve, Vth-variability",

author = "Shigeki Ohbayashi and Makoto Yabuuchi and Koji Nil and Yasumasa Tsukamoto and Susumu Imaoka and Yuji Oda and Tsutomu Yoshihara and Motoshige Igarashi and Masahiko Takeuchi and Hiroshi Kawashima and Yasuo Yamaguchi and Kazuhiro Tsukamoto and Masahide Inuishi and Hiroshi Makino and Koichiro Ishibashi and Hirofumi Shinohara",

year = "2007",

month = apr,

doi = "10.1109/JSSC.2007.891648",

language = "English",

volume = "42",

pages = "820--829",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

AU - Ohbayashi, Shigeki

AU - Yabuuchi, Makoto

AU - Nil, Koji

AU - Tsukamoto, Yasumasa

AU - Imaoka, Susumu

AU - Oda, Yuji

AU - Yoshihara, Tsutomu

AU - Igarashi, Motoshige

AU - Takeuchi, Masahiko

AU - Kawashima, Hiroshi

AU - Yamaguchi, Yasuo

AU - Tsukamoto, Kazuhiro

AU - Inuishi, Masahide

AU - Makino, Hiroshi

AU - Ishibashi, Koichiro

AU - Shinohara, Hirofumi

PY - 2007/4

Y1 - 2007/4

N2 - In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-μm2 SRAM cell with a β ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.

AB - In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-μm2 SRAM cell with a β ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.

KW - 65-nm CMOS

KW - 6T-SRAM

KW - Assist circuit

KW - CMOS

KW - Embedded SRAM

KW - SRAM

KW - Vth curve

KW - Vth-variability

UR - http://www.scopus.com/inward/record.url?scp=33947613119&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33947613119&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2007.891648

DO - 10.1109/JSSC.2007.891648

M3 - Article

AN - SCOPUS:33947613119

SN - 0018-9200

VL - 42

SP - 820

EP - 829

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 4

ER -

A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this