A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

Shigeki Ohbayashi*, Makoto Yabuuchi, Koji Nil, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

98 Citations (Scopus)

Abstract

In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-μm2 SRAM cell with a β ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.

Original languageEnglish
Pages (from-to)820-829
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume42
Issue number4
DOIs
Publication statusPublished - 2007 Apr
Externally publishedYes

Keywords

  • 65-nm CMOS
  • 6T-SRAM
  • Assist circuit
  • CMOS
  • Embedded SRAM
  • SRAM
  • Vth curve
  • Vth-variability

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits'. Together they form a unique fingerprint.

Cite this