A 65 nm ultra-high-density dual-port SRAM with 0.71um2 8T-cell for SoC

K. Nii*, Y. Masuda, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, M. Igarashi, K. Tomita, N. Tsuboi, H. Makino, K. Ishibashi, H. Shinohara

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Citations (Scopus)


We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71um2 8T-DP-cell, which cell size is 1.44x larger than 6T-single-port (SP)-cell.

Original languageEnglish
Title of host publication2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Number of pages2
Publication statusPublished - 2006 Dec 1
Externally publishedYes
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: 2006 Jun 152006 Jun 17

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers


Other2006 Symposium on VLSI Circuits, VLSIC
Country/TerritoryUnited States
CityHonolulu, HI


  • 65nm
  • 8T-cell SNM
  • Dual-port
  • Hp90
  • SEAM
  • SoC

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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