A 65 nm ultra-high-density dual-port SRAM with 0.71um2 8T-cell for SoC

K. Nii, Y. Masuda, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, M. Igarashi, K. Tomita, N. Tsuboi, H. Makino, K. Ishibashi, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71um2 8T-DP-cell, which cell size is 1.44x larger than 6T-single-port (SP)-cell.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages130-131
Number of pages2
Publication statusPublished - 2006
Externally publishedYes
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: 2006 Jun 152006 Jun 17

Other

Other2006 Symposium on VLSI Circuits, VLSIC
CountryUnited States
CityHonolulu, HI
Period06/6/1506/6/17

Fingerprint

Static random access storage
Macros
Networks (circuits)
System-on-chip

Keywords

  • 65nm
  • 8T-cell SNM
  • Dual-port
  • Hp90
  • SEAM
  • SoC

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Nii, K., Masuda, Y., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Imaoka, S., ... Shinohara, H. (2006). A 65 nm ultra-high-density dual-port SRAM with 0.71um2 8T-cell for SoC. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 130-131). [1705344]

A 65 nm ultra-high-density dual-port SRAM with 0.71um2 8T-cell for SoC. / Nii, K.; Masuda, Y.; Yabuuchi, M.; Tsukamoto, Y.; Ohbayashi, S.; Imaoka, S.; Igarashi, M.; Tomita, K.; Tsuboi, N.; Makino, H.; Ishibashi, K.; Shinohara, Hirofumi.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2006. p. 130-131 1705344.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nii, K, Masuda, Y, Yabuuchi, M, Tsukamoto, Y, Ohbayashi, S, Imaoka, S, Igarashi, M, Tomita, K, Tsuboi, N, Makino, H, Ishibashi, K & Shinohara, H 2006, A 65 nm ultra-high-density dual-port SRAM with 0.71um2 8T-cell for SoC. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 1705344, pp. 130-131, 2006 Symposium on VLSI Circuits, VLSIC, Honolulu, HI, United States, 06/6/15.
Nii K, Masuda Y, Yabuuchi M, Tsukamoto Y, Ohbayashi S, Imaoka S et al. A 65 nm ultra-high-density dual-port SRAM with 0.71um2 8T-cell for SoC. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2006. p. 130-131. 1705344
Nii, K. ; Masuda, Y. ; Yabuuchi, M. ; Tsukamoto, Y. ; Ohbayashi, S. ; Imaoka, S. ; Igarashi, M. ; Tomita, K. ; Tsuboi, N. ; Makino, H. ; Ishibashi, K. ; Shinohara, Hirofumi. / A 65 nm ultra-high-density dual-port SRAM with 0.71um2 8T-cell for SoC. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2006. pp. 130-131
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