A 65 nm ultra-high-density dual-port SRAM with 0.71um2 8T-cell for SoC

K. Nii; Y. Masuda; M. Yabuuchi; Y. Tsukamoto; S. Ohbayashi; S. Imaoka; M. Igarashi; K. Tomita; N. Tsuboi; H. Makino; K. Ishibashi; H. Shinohara

A 65 nm ultra-high-density dual-port SRAM with 0.71um² 8T-cell for SoC

K. Nii^*, Y. Masuda, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, M. Igarashi, K. Tomita, N. Tsuboi, H. Makino, K. Ishibashi, H. Shinohara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

20 Citations (Scopus)

Abstract

We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71um² 8T-DP-cell, which cell size is 1.44x larger than 6T-single-port (SP)-cell.

Original language	English
Title of host publication	2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages	130-131
Number of pages	2
Publication status	Published - 2006 Dec 1
Externally published	Yes
Event	2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States Duration: 2006 Jun 15 → 2006 Jun 17

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2006 Symposium on VLSI Circuits, VLSIC
Country/Territory	United States
City	Honolulu, HI
Period	06/6/15 → 06/6/17

Keywords

65nm
8T-cell SNM
Dual-port
Hp90
SEAM
SoC

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Nii, K., Masuda, Y., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Imaoka, S., Igarashi, M., Tomita, K., Tsuboi, N., Makino, H., Ishibashi, K., & Shinohara, H. (2006). A 65 nm ultra-high-density dual-port SRAM with 0.71um² 8T-cell for SoC. In 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers (pp. 130-131). [1705344] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Nii, K, Masuda, Y, Yabuuchi, M, Tsukamoto, Y, Ohbayashi, S, Imaoka, S, Igarashi, M, Tomita, K, Tsuboi, N, Makino, H, Ishibashi, K & Shinohara, H 2006, A 65 nm ultra-high-density dual-port SRAM with 0.71um² 8T-cell for SoC. in 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers., 1705344, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 130-131, 2006 Symposium on VLSI Circuits, VLSIC, Honolulu, HI, United States, 06/6/15.

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abstract = "We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71um2 8T-DP-cell, which cell size is 1.44x larger than 6T-single-port (SP)-cell.",

keywords = "65nm, 8T-cell SNM, Dual-port, Hp90, SEAM, SoC",

author = "K. Nii and Y. Masuda and M. Yabuuchi and Y. Tsukamoto and S. Ohbayashi and S. Imaoka and M. Igarashi and K. Tomita and N. Tsuboi and H. Makino and K. Ishibashi and H. Shinohara",

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AU - Nii, K.

AU - Masuda, Y.

AU - Yabuuchi, M.

AU - Tsukamoto, Y.

AU - Ohbayashi, S.

AU - Imaoka, S.

AU - Igarashi, M.

AU - Tomita, K.

AU - Tsuboi, N.

AU - Makino, H.

AU - Ishibashi, K.

AU - Shinohara, H.

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AB - We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71um2 8T-DP-cell, which cell size is 1.44x larger than 6T-single-port (SP)-cell.

KW - 65nm

KW - 8T-cell SNM

KW - Dual-port

KW - Hp90

KW - SEAM

KW - SoC

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