A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die

Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Qkada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
Duration: 2007 Feb 112007 Feb 15

Other

Other54th IEEE International Solid-State Circuits Conference, ISSCC 2007
CountryUnited States
CitySan Francisco, CA
Period07/2/1107/2/15

Fingerprint

Static random access storage
Electric fuses
Redundancy
Repair
System-on-chip

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Ohbayashi, S., Yabuuchi, M., Kono, K., Oda, Y., Imaoka, S., Usui, K., ... Shinohara, H. (2007). A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference [4242478] https://doi.org/10.1109/ISSCC.2007.373507

A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. / Ohbayashi, Shigeki; Yabuuchi, Makoto; Kono, Kazushi; Oda, Yuji; Imaoka, Susumu; Usui, Keiichi; Yonezu, Toshiaki; Iwamoto, Takeshi; Nii, Koji; Tsukamoto, Yasumasa; Arakawa, Masashi; Uchida, Takahiro; Qkada, Masakazu; Ishii, Atsushi; Makino, Hiroshi; Ishibashi, Koichiro; Shinohara, Hirofumi.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2007. 4242478.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ohbayashi, S, Yabuuchi, M, Kono, K, Oda, Y, Imaoka, S, Usui, K, Yonezu, T, Iwamoto, T, Nii, K, Tsukamoto, Y, Arakawa, M, Uchida, T, Qkada, M, Ishii, A, Makino, H, Ishibashi, K & Shinohara, H 2007, A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference., 4242478, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, CA, United States, 07/2/11. https://doi.org/10.1109/ISSCC.2007.373507
Ohbayashi S, Yabuuchi M, Kono K, Oda Y, Imaoka S, Usui K et al. A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2007. 4242478 https://doi.org/10.1109/ISSCC.2007.373507
Ohbayashi, Shigeki ; Yabuuchi, Makoto ; Kono, Kazushi ; Oda, Yuji ; Imaoka, Susumu ; Usui, Keiichi ; Yonezu, Toshiaki ; Iwamoto, Takeshi ; Nii, Koji ; Tsukamoto, Yasumasa ; Arakawa, Masashi ; Uchida, Takahiro ; Qkada, Masakazu ; Ishii, Atsushi ; Makino, Hiroshi ; Ishibashi, Koichiro ; Shinohara, Hirofumi. / A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2007.
@inproceedings{8d917ec07b4e45cfb11ee505ccf82ba6,
title = "A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die",
abstract = "A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2{\%}.",
author = "Shigeki Ohbayashi and Makoto Yabuuchi and Kazushi Kono and Yuji Oda and Susumu Imaoka and Keiichi Usui and Toshiaki Yonezu and Takeshi Iwamoto and Koji Nii and Yasumasa Tsukamoto and Masashi Arakawa and Takahiro Uchida and Masakazu Qkada and Atsushi Ishii and Hiroshi Makino and Koichiro Ishibashi and Hirofumi Shinohara",
year = "2007",
doi = "10.1109/ISSCC.2007.373507",
language = "English",
isbn = "1424408539",
booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

}

TY - GEN

T1 - A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die

AU - Ohbayashi, Shigeki

AU - Yabuuchi, Makoto

AU - Kono, Kazushi

AU - Oda, Yuji

AU - Imaoka, Susumu

AU - Usui, Keiichi

AU - Yonezu, Toshiaki

AU - Iwamoto, Takeshi

AU - Nii, Koji

AU - Tsukamoto, Yasumasa

AU - Arakawa, Masashi

AU - Uchida, Takahiro

AU - Qkada, Masakazu

AU - Ishii, Atsushi

AU - Makino, Hiroshi

AU - Ishibashi, Koichiro

AU - Shinohara, Hirofumi

PY - 2007

Y1 - 2007

N2 - A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%.

AB - A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%.

UR - http://www.scopus.com/inward/record.url?scp=34548841112&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34548841112&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2007.373507

DO - 10.1109/ISSCC.2007.373507

M3 - Conference contribution

AN - SCOPUS:34548841112

SN - 1424408539

SN - 9781424408535

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

ER -