A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM

Takeshi Hamamoto*, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

31 Citations (Scopus)


This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-μm DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.

Original languageEnglish
Pages (from-to)194-206
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Issue number1
Publication statusPublished - 2004 Jan
Externally publishedYes


  • Delay lines
  • Delay-locked loops (DLLs)
  • DRAM chips
  • High-speed techniques
  • Jitter

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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