Abstract
This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-μm DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.
| Original language | English |
|---|---|
| Pages (from-to) | 194-206 |
| Number of pages | 13 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 39 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 2004 Jan |
| Externally published | Yes |
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Keywords
- Delay lines
- Delay-locked loops (DLLs)
- DRAM chips
- High-speed techniques
- Jitter
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM. / Hamamoto, Takeshi; Furutani, Kiyohiro; Kubo, Takashi; Kawasaki, Satoshi; Iga, Hironori; Kono, Takashi; Konishi, Yasuhiro; Yoshihara, Tsutomu.
In: IEEE Journal of Solid-State Circuits, Vol. 39, No. 1, 01.2004, p. 194-206.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM
AU - Hamamoto, Takeshi
AU - Furutani, Kiyohiro
AU - Kubo, Takashi
AU - Kawasaki, Satoshi
AU - Iga, Hironori
AU - Kono, Takashi
AU - Konishi, Yasuhiro
AU - Yoshihara, Tsutomu
PY - 2004/1
Y1 - 2004/1
N2 - This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-μm DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.
AB - This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-μm DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.
KW - Delay lines
KW - Delay-locked loops (DLLs)
KW - DRAM chips
KW - High-speed techniques
KW - Jitter
UR - http://www.scopus.com/inward/record.url?scp=0742286337&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0742286337&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2003.820851
DO - 10.1109/JSSC.2003.820851
M3 - Article
AN - SCOPUS:0742286337
VL - 39
SP - 194
EP - 206
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 1
ER -