A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM

Takeshi Hamamoto; Kiyohiro Furutani; Takashi Kubo; Satoshi Kawasaki; Hironori Iga; Takashi Kono; Yasuhiro Konishi; Tsutomu Yoshihara

doi:10.1109/JSSC.2003.820851

A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM

Takeshi Hamamoto, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara

Research output: Contribution to journal › Article

30 Citations (Scopus)

Abstract

This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-μm DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.

Original language	English
Pages (from-to)	194-206
Number of pages	13
Journal	IEEE Journal of Solid-State Circuits
Volume	39
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2003.820851
Publication status	Published - 2004 Jan
Externally published	Yes

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Keywords

Delay lines
Delay-locked loops (DLLs)
DRAM chips
High-speed techniques
Jitter

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Hamamoto, T., Furutani, K., Kubo, T., Kawasaki, S., Iga, H., Kono, T., Konishi, Y., & Yoshihara, T. (2004). A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM. IEEE Journal of Solid-State Circuits, 39(1), 194-206. https://doi.org/10.1109/JSSC.2003.820851

@article{a5fb00416918434cb8074913f3252437,

title = "A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM",

abstract = "This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-μm DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.",

keywords = "Delay lines, Delay-locked loops (DLLs), DRAM chips, High-speed techniques, Jitter",

author = "Takeshi Hamamoto and Kiyohiro Furutani and Takashi Kubo and Satoshi Kawasaki and Hironori Iga and Takashi Kono and Yasuhiro Konishi and Tsutomu Yoshihara",

year = "2004",

month = jan

doi = "10.1109/JSSC.2003.820851",

language = "English",

volume = "39",

pages = "194--206",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM

AU - Hamamoto, Takeshi

AU - Furutani, Kiyohiro

AU - Kubo, Takashi

AU - Kawasaki, Satoshi

AU - Iga, Hironori

AU - Kono, Takashi

AU - Konishi, Yasuhiro

AU - Yoshihara, Tsutomu

PY - 2004/1

Y1 - 2004/1

N2 - This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-μm DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.

AB - This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-μm DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.

KW - Delay lines

KW - Delay-locked loops (DLLs)

KW - DRAM chips

KW - High-speed techniques

KW - Jitter

UR - http://www.scopus.com/inward/record.url?scp=0742286337&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0742286337&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2003.820851

DO - 10.1109/JSSC.2003.820851

M3 - Article

AN - SCOPUS:0742286337

VL - 39

SP - 194

EP - 206

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 1

ER -

Access to Document

10.1109/JSSC.2003.820851