Abstract
This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-μm DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.
Original language | English |
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Pages (from-to) | 194-206 |
Number of pages | 13 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 39 |
Issue number | 1 |
DOIs | |
Publication status | Published - 2004 Jan |
Externally published | Yes |
Keywords
- Delay lines
- Delay-locked loops (DLLs)
- DRAM chips
- High-speed techniques
- Jitter
ASJC Scopus subject areas
- Electrical and Electronic Engineering