A 6.72-Gb/s 8pJ/bit/iteration IEEE 802.15.3c LDPC decoder chip

Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Qian Xie, Leona Okamura, Dajiang Zhou, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)

    Abstract

    In this paper, we introduce an LDPC decoder design for decoding length-672 code adopted in IEEE 802.15.3c standard. The proposed decoder features high performance in both data rate and power efficiency. A macro-layer level fully parallel layered decoding architecture is proposed to support the throughput requirement in the standard. The decoder takes only 4 clock cycles to process one decoding iteration. While parallelism increases, the chip routing congestion problem becomes more severe because of the more complicated interconnection network used for message passing. This problem is nicely solved by our proposed efficient message permutation scheme utilizing the parity check matrix features. The proposed message permutation network features high compatibility and zero-logic-gate VLSI implementation, which contribute to the remarkable improvements in both area utilization ratio and total gate count. To verify the above techniques, the proposed decoder is implemented on a chip fabricated using Fujitsu 65nm 1P12L LVT CMOS process. The chip occupies a core area of 1.30mm 2 with area utilization ratio 86.3%. According to the measurement results, working at 1.2V, 400 MHz and 10 iterations the proposed decoder delivers a 6.72Gb/s data throughput and dissipates a power of 537.6mW, resulting in an energy efficiency 8.0pJ/bit/iteration.

    Original languageEnglish
    Title of host publication2011 International Symposium on Integrated Circuits, ISIC 2011
    Pages7-12
    Number of pages6
    DOIs
    Publication statusPublished - 2011
    Event2011 International Symposium on Integrated Circuits, ISIC 2011 - SingaporeSingapore
    Duration: 2011 Dec 122011 Dec 14

    Other

    Other2011 International Symposium on Integrated Circuits, ISIC 2011
    CitySingaporeSingapore
    Period11/12/1211/12/14

    Fingerprint

    Decoding
    Throughput
    Logic gates
    Message passing
    Energy efficiency
    Macros
    Clocks

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Chen, Z., Peng, X., Zhao, X., Xie, Q., Okamura, L., Zhou, D., & Goto, S. (2011). A 6.72-Gb/s 8pJ/bit/iteration IEEE 802.15.3c LDPC decoder chip. In 2011 International Symposium on Integrated Circuits, ISIC 2011 (pp. 7-12). [6131868] https://doi.org/10.1109/ISICir.2011.6131868

    A 6.72-Gb/s 8pJ/bit/iteration IEEE 802.15.3c LDPC decoder chip. / Chen, Zhixiang; Peng, Xiao; Zhao, Xiongxin; Xie, Qian; Okamura, Leona; Zhou, Dajiang; Goto, Satoshi.

    2011 International Symposium on Integrated Circuits, ISIC 2011. 2011. p. 7-12 6131868.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Chen, Z, Peng, X, Zhao, X, Xie, Q, Okamura, L, Zhou, D & Goto, S 2011, A 6.72-Gb/s 8pJ/bit/iteration IEEE 802.15.3c LDPC decoder chip. in 2011 International Symposium on Integrated Circuits, ISIC 2011., 6131868, pp. 7-12, 2011 International Symposium on Integrated Circuits, ISIC 2011, SingaporeSingapore, 11/12/12. https://doi.org/10.1109/ISICir.2011.6131868
    Chen Z, Peng X, Zhao X, Xie Q, Okamura L, Zhou D et al. A 6.72-Gb/s 8pJ/bit/iteration IEEE 802.15.3c LDPC decoder chip. In 2011 International Symposium on Integrated Circuits, ISIC 2011. 2011. p. 7-12. 6131868 https://doi.org/10.1109/ISICir.2011.6131868
    Chen, Zhixiang ; Peng, Xiao ; Zhao, Xiongxin ; Xie, Qian ; Okamura, Leona ; Zhou, Dajiang ; Goto, Satoshi. / A 6.72-Gb/s 8pJ/bit/iteration IEEE 802.15.3c LDPC decoder chip. 2011 International Symposium on Integrated Circuits, ISIC 2011. 2011. pp. 7-12
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