A 6.72-Gb/s 8pJ/bit/iteration IEEE 802.15.3c LDPC decoder chip

Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto

    Research output: Contribution to journalArticle

    1 Citation (Scopus)

    Abstract

    In this paper, we introduce an LDPC decoder design for decoding a length-672 multi-rate code adopted in IEEE 802.15.3c standard. The proposed decoder features high performances in both data rate and power efficiency. A macro-layer level fully parallel layered decoding architecture is proposed to support the throughput requirement in the standard. For the proposed decoder, it takes only 4 clock cycles to process one decoding iteration. While parallelism increases, the chip routing congestion problem becomes more severe because a more complicated interconnection network is needed for message passing during the decoding process. This problem is nicely solved by our proposed efficient message permutation scheme utilizing exploited parity check matrix features. The proposed message permutation network features high compatibility and zero-logic-gate VLSI implementation, which contribute to the remarkable improvements in both area utilization ratio and total gate count. Meanwhile, frame-level pipeline decoding is applied in the design to shorten the critical path. To verify the above techniques, the proposed decoder is implemented on a chip fabricated using Fujitsu 65 nm 1P12L LVT CMOS process. The chip occupies a core area of 1.30mm2 with area utilization ratio 86.3%. According to the measurement results, working at 1.2V, 400MHz and 10 iterations the proposed decoder delivers a 6.72 Gb/s data throughput and dissipates a power of 537.6mW, resulting in an energy efficiency 8.0 pJ/bit/iteration. Moreover, a decoder of the same architecture but with no pipeline stage for low-profile application is also implemented and evaluated at post-layout level.

    Original languageEnglish
    Pages (from-to)2587-2596
    Number of pages10
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE94-A
    Issue number12
    DOIs
    Publication statusPublished - 2011 Dec

    Fingerprint

    Decoding
    Chip
    Iteration
    Permutation
    Throughput
    Pipelines
    Dissipate
    Critical Path
    Logic gates
    Interconnection Networks
    Message passing
    Message Passing
    Energy Efficiency
    Congestion
    Compatibility
    Parity
    Parallelism
    Energy efficiency
    Macros
    Layout

    Keywords

    • High data rate
    • IEEE802.15.3c
    • LDPC decoder
    • Powerefficient
    • WPAN

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

    Cite this

    A 6.72-Gb/s 8pJ/bit/iteration IEEE 802.15.3c LDPC decoder chip. / Chen, Zhixiang; Peng, Xiao; Zhao, Xiongxin; Okamura, Leona; Zhou, Dajiang; Goto, Satoshi.

    In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E94-A, No. 12, 12.2011, p. 2587-2596.

    Research output: Contribution to journalArticle

    Chen, Zhixiang ; Peng, Xiao ; Zhao, Xiongxin ; Okamura, Leona ; Zhou, Dajiang ; Goto, Satoshi. / A 6.72-Gb/s 8pJ/bit/iteration IEEE 802.15.3c LDPC decoder chip. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2011 ; Vol. E94-A, No. 12. pp. 2587-2596.
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