A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS

Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    An LDPC decoder in 65nm CMOS targeting WPAN (IEEE 802.15.3c) is presented with measurement results. A modified-PCM based message permutation strategy with compatible data flow is proposed to solve the network problem raised by high parallelism LDPC decoding. Compared to the state-of-art, decoder chip achieves 17.7%, 33.5% and 49% improvements in chip density, gate count and energy efficiency, respectively.

    Original languageEnglish
    Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    Pages87-88
    Number of pages2
    DOIs
    Publication statusPublished - 2013
    Event2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 - Yokohama
    Duration: 2013 Jan 222013 Jan 25

    Other

    Other2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
    CityYokohama
    Period13/1/2213/1/25

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design

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  • Cite this

    Chen, Z., Peng, X., Zhao, X., Okamura, L., Zhou, D., & Goto, S. (2013). A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 87-88). [6509569] https://doi.org/10.1109/ASPDAC.2013.6509569