A 7-Die 3D Stacked 3840 × 2160@120 fps motion estimation processor

Shuping Zhang, Jinjia Zhou, Dajiang Zhou, Shinji Kimura, Satoshi Goto

Research output: Contribution to journalArticle

Abstract

In this paper, a hamburger architecture with a 3D stacked reconfigurable memory is proposed for a 4K motion estimation (ME) processor. By positioning the memory dies on both the top and bottom sides of the processor die, the proposed hamburger architecture can reduce the usage of the signal through-silicon via (TSV), and balance the power delivery network and the clock tree of the entire system. It results in 1/3 reduction of the usage of signal TSVs. Moreover, a stacked reconfigurable memory architecture is proposed to reduce the fabrication complexity and further reduce the number of signal TSVs by more than 1/2. The reduction of signal TSVs in the entire design is 71.24%. Finally, we address unique issues that occur in electronic design automation (EDA) tools during 3D largescale integration (LSI) designs. As a result, a 4K ME processor with 7-die stacking 3D system-on-chip design is implemented. The proposed design can support real time 3840 × 2160 @ 120 fps encoding at 130 MHz with less than 540 mW.

Original languageEnglish
Pages (from-to)223-231
Number of pages9
JournalIEICE Transactions on Electronics
VolumeE100C
Issue number3
DOIs
Publication statusPublished - 2017 Mar

Keywords

  • 3D IC design
  • Hamburger architecture
  • Memory stacking
  • Motion estimation processor

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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