SIFT, short for Scale Invariant Feature Transform, is regarded as one of the most robust feature detection algorithms. The Gaussian and DoG Pyramid Construction part, functioning as computation basis and searching spaces for other parts, proves fatal to the system. In this paper, we present an FPGA-implementable hardware accelerator for this part. Stratified Gaussian Convolution scheme and 7-Round Parallel Computation scheme are introduced to reduce the hardware cost and improve process speed, meanwhile keeping high accuracy. In our experiment, our proposal successfully realizes a system with max clock frequency of 95.0 MHz, and on-system process speed of up to 21 fps for VGA format images. Hardware cost of Slice LUTs is reduced by 12.1% compared with traditional work. Accuracy is kept as high as 98.27% against original software solution. Our proposed structure proves to be suitable for real-time SIFT systems.