A 98 GMACs/W 32-core vector processor in 65nm CMOS

Xun He; Dajiang Zhou; Xin Jin; Satoshi Goto

doi:10.1109/ISLPED.2011.5993669

A 98 GMACs/W 32-core vector processor in 65nm CMOS

Xun He^*, Dajiang Zhou, Xin Jin, Satoshi Goto

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. The proposed hierarchical network can provide 192 GB/sintercore communication BW in average. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Comparing with MOESI, 67.8% of L1 Cache energy can be saved in 32 cores case. It can achieve a peak performance of 375 GMACs and 98 GMACs/W in 65 nm CMOS.

Original language	English
Title of host publication	Proceedings of the International Symposium on Low Power Electronics and Design
Pages	373-378
Number of pages	6
DOIs	https://doi.org/10.1109/ISLPED.2011.5993669
Publication status	Published - 2011
Event	17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka Duration: 2011 Aug 1 → 2011 Aug 3

Other

Other	17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
City	Fukuoka
Period	11/8/1 → 11/8/3

Keywords

Cache coherence
Multicore Processor
NoC
SIMD

ASJC Scopus subject areas

Engineering(all)

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10.1109/ISLPED.2011.5993669

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title = "A 98 GMACs/W 32-core vector processor in 65nm CMOS",

abstract = "This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. The proposed hierarchical network can provide 192 GB/sintercore communication BW in average. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Comparing with MOESI, 67.8% of L1 Cache energy can be saved in 32 cores case. It can achieve a peak performance of 375 GMACs and 98 GMACs/W in 65 nm CMOS.",

keywords = "Cache coherence, Multicore Processor, NoC, SIMD",

author = "Xun He and Dajiang Zhou and Xin Jin and Satoshi Goto",

year = "2011",

doi = "10.1109/ISLPED.2011.5993669",

language = "English",

isbn = "9781612846590",

pages = "373--378",

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AU - He, Xun

AU - Zhou, Dajiang

AU - Jin, Xin

AU - Goto, Satoshi

PY - 2011

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N2 - This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. The proposed hierarchical network can provide 192 GB/sintercore communication BW in average. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Comparing with MOESI, 67.8% of L1 Cache energy can be saved in 32 cores case. It can achieve a peak performance of 375 GMACs and 98 GMACs/W in 65 nm CMOS.

AB - This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. The proposed hierarchical network can provide 192 GB/sintercore communication BW in average. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Comparing with MOESI, 67.8% of L1 Cache energy can be saved in 32 cores case. It can achieve a peak performance of 375 GMACs and 98 GMACs/W in 65 nm CMOS.

KW - Cache coherence

KW - Multicore Processor

KW - NoC

KW - SIMD

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BT - Proceedings of the International Symposium on Low Power Electronics and Design

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ER -

A 98 GMACs/W 32-core vector processor in 65nm CMOS

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Keywords

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