A behavior-based reconfigurable cache for the low-power embedded processor

Jiongyao Ye, Jiannan Jin, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In embedded processor designs, a cache becomes the main contributor of the power consumption as it greatly improves the performance. The conventional low-power techniques of a cache based on a fixed hardware configuration cannot be configured and it is independent on the program behavior. Thus, a configurable cache is proposed to save energy and improve performance by dynamically adjusting the cache parameters for the code that is executing. However, most existing configurable caches explore and adapt the optimal configuration based on successive time-intervals, which presents efficiency only if the program can keep its execution phase for a number of intervals. In this paper, we propose a behavior-based configurable cache, which can be dynamically adjusted based on the program behavior. The design adds very little hardware complexity and commits most workload to the software, so that it is very effective for the embedded microprocessors design. Simulation by using Spec 2000 shows that our proposed configurable cache can reduce the power consumption by up to 60.6% and 22.3% compared to a conventional set-associative cache and a temporal-based configurable cache, respectively. At the same time, performance degradation is about 0.75%.

Original languageEnglish
Title of host publicationProceedings of International Conference on ASIC
Pages1-5
Number of pages5
DOIs
Publication statusPublished - 2011
Event2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen
Duration: 2011 Oct 252011 Oct 28

Other

Other2011 IEEE 9th International Conference on ASIC, ASICON 2011
CityXiamen
Period11/10/2511/10/28

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ye, J., Jin, J., & Watanabe, T. (2011). A behavior-based reconfigurable cache for the low-power embedded processor. In Proceedings of International Conference on ASIC (pp. 1-5). [6157107] https://doi.org/10.1109/ASICON.2011.6157107