A bit-write reduction method based on error-correcting codes for non-volatile memories

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Non-volatile memory has many advantages over SRAM. However, one of its largest problems is that it consumes a large amount of energy in writing. In this paper, we propose a bit-write reduction method based on error correcting codes for non-volatile memories. When a data is written into a memory cell, we do not write it directly but encode it into a codeword. We focus on error-correcting codes and generate new codes called write-reduction codes. In our write-reduction codes, each data corresponds to an information vector in an error-correcting code and an information vector corresponds not to a single codeword but a set of write-reduction codewords. Given a writing data and current memory bits, we can deterministically select a particular write-reduction codeword corresponding to a data to be written, where the maximum number of flipped bits are theoretically minimized. Then the number of writing bits into memory cells will also be minimized. We perform several experimental evaluations and demonstrate up to 72% energy reduction.

Original languageEnglish
Title of host publication20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages496-501
Number of pages6
ISBN (Print)9781479977925
DOIs
Publication statusPublished - 2015 Mar 11
Event2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan
Duration: 2015 Jan 192015 Jan 22

Other

Other2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
CountryJapan
CityChiba
Period15/1/1915/1/22

Fingerprint

Error-correcting Codes
Reduction Method
Data storage equipment
Cell
Energy
Experimental Evaluation
Static random access storage
Demonstrate

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Control and Systems Engineering
  • Modelling and Simulation

Cite this

Tawada, M., Kimura, S., Yanagisawa, M., & Togawa, N. (2015). A bit-write reduction method based on error-correcting codes for non-volatile memories. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 496-501). [7059055] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7059055

A bit-write reduction method based on error-correcting codes for non-volatile memories. / Tawada, Masashi; Kimura, Shinji; Yanagisawa, Masao; Togawa, Nozomu.

20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 496-501 7059055.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tawada, M, Kimura, S, Yanagisawa, M & Togawa, N 2015, A bit-write reduction method based on error-correcting codes for non-volatile memories. in 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7059055, Institute of Electrical and Electronics Engineers Inc., pp. 496-501, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, 15/1/19. https://doi.org/10.1109/ASPDAC.2015.7059055
Tawada M, Kimura S, Yanagisawa M, Togawa N. A bit-write reduction method based on error-correcting codes for non-volatile memories. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 496-501. 7059055 https://doi.org/10.1109/ASPDAC.2015.7059055
Tawada, Masashi ; Kimura, Shinji ; Yanagisawa, Masao ; Togawa, Nozomu. / A bit-write reduction method based on error-correcting codes for non-volatile memories. 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 496-501
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