TY - GEN
T1 - A bit-write reduction method based on error-correcting codes for non-volatile memories
AU - Tawada, Masashi
AU - Kimura, Shinji
AU - Yanagisawa, Masao
AU - Togawa, Nozomu
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/3/11
Y1 - 2015/3/11
N2 - Non-volatile memory has many advantages over SRAM. However, one of its largest problems is that it consumes a large amount of energy in writing. In this paper, we propose a bit-write reduction method based on error correcting codes for non-volatile memories. When a data is written into a memory cell, we do not write it directly but encode it into a codeword. We focus on error-correcting codes and generate new codes called write-reduction codes. In our write-reduction codes, each data corresponds to an information vector in an error-correcting code and an information vector corresponds not to a single codeword but a set of write-reduction codewords. Given a writing data and current memory bits, we can deterministically select a particular write-reduction codeword corresponding to a data to be written, where the maximum number of flipped bits are theoretically minimized. Then the number of writing bits into memory cells will also be minimized. We perform several experimental evaluations and demonstrate up to 72% energy reduction.
AB - Non-volatile memory has many advantages over SRAM. However, one of its largest problems is that it consumes a large amount of energy in writing. In this paper, we propose a bit-write reduction method based on error correcting codes for non-volatile memories. When a data is written into a memory cell, we do not write it directly but encode it into a codeword. We focus on error-correcting codes and generate new codes called write-reduction codes. In our write-reduction codes, each data corresponds to an information vector in an error-correcting code and an information vector corresponds not to a single codeword but a set of write-reduction codewords. Given a writing data and current memory bits, we can deterministically select a particular write-reduction codeword corresponding to a data to be written, where the maximum number of flipped bits are theoretically minimized. Then the number of writing bits into memory cells will also be minimized. We perform several experimental evaluations and demonstrate up to 72% energy reduction.
UR - http://www.scopus.com/inward/record.url?scp=84926442585&partnerID=8YFLogxK
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U2 - 10.1109/ASPDAC.2015.7059055
DO - 10.1109/ASPDAC.2015.7059055
M3 - Conference contribution
AN - SCOPUS:84926442585
T3 - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
SP - 496
EP - 501
BT - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Y2 - 19 January 2015 through 22 January 2015
ER -