A bitwidth-aware high-level synthesis algorithm using operation chainings for tiled-DR architectures

    Research output: Contribution to journalArticle

    Abstract

    As application hardware designs and implementations in a short term are required, high-level synthesis is more and more essential EDA technique nowadays. In deep-submicron era, interconnection delays are not negligible even in high-level synthesis thus distributed-register and - controller architectures (DR architectures) have been proposed in order to cope with this problem. It is also profitable to take data-bitwidth into account in high-level synthesis. In this paper, we propose a bitwidth-aware high-level synthesis algorithm using operation chainings targeting Tiled-DR architectures. Our proposed algorithm optimizes bitwidths of functional units and utilizes the vacant tiles by adding some extra functional units to realize effective operation chainings to generate high performance circuits without increasing the total area. Experimental results show that our proposed algorithm reduces the overall latency by up to 47% comparedtothe conventional approach without area overheads by eliminating unnecessary bitwidths and adding efficient extra FUs for Tiled-DR architectures.

    Original languageEnglish
    Pages (from-to)2911-2924
    Number of pages14
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE100A
    Issue number12
    DOIs
    Publication statusPublished - 2017 Dec 1

    Keywords

    • Distributed-register architecture
    • Floorplan
    • High-level synthesis
    • Interconnection delay
    • Multiple-bitwidth
    • Operation chaining

    ASJC Scopus subject areas

    • Signal Processing
    • Computer Graphics and Computer-Aided Design
    • Electrical and Electronic Engineering
    • Applied Mathematics

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