A CABAC encoding core with dynamic pipeline for H.264/AVC main profile

Lingfeng Li, Yang Song, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)

Abstract

This paper presents an encoder core architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) in H.264/AVC main profile. The throughput of CABAC encoder is usually limited due to i) bit-wise processing, ii) complicated data dependency, and iii) variant iteration times for each binary symbol. This paper adopts dynamic pipeline scheme to improve the performance of CABAC encoder. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Meanwhile, pipeline bypass scheme is applied to eliminate the possible memory conflict Proposed encoder core is implemented under ROHM 0.35μm technology. Results show that the equivalent gate counts is 4.57k when the maximum frequency is 150MHz. It is estimated that the proposed CABAC encoding core can process the input binary symbol at a bit-rate of 80Mb/s.

Original languageEnglish
Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Pages760-763
Number of pages4
DOIs
Publication statusPublished - 2006
EventAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems -
Duration: 2006 Dec 42006 Dec 6

Other

OtherAPCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
Period06/12/406/12/6

Fingerprint

Pipelines
Throughput
Data storage equipment
Processing

Keywords

  • Architecture
  • CABAC
  • H.264
  • Pipeline

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Li, L., Song, Y., Ikenaga, T., & Goto, S. (2006). A CABAC encoding core with dynamic pipeline for H.264/AVC main profile. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (pp. 760-763). [4145504] https://doi.org/10.1109/APCCAS.2006.342119

A CABAC encoding core with dynamic pipeline for H.264/AVC main profile. / Li, Lingfeng; Song, Yang; Ikenaga, Takeshi; Goto, Satoshi.

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2006. p. 760-763 4145504.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Li, L, Song, Y, Ikenaga, T & Goto, S 2006, A CABAC encoding core with dynamic pipeline for H.264/AVC main profile. in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS., 4145504, pp. 760-763, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 06/12/4. https://doi.org/10.1109/APCCAS.2006.342119
Li L, Song Y, Ikenaga T, Goto S. A CABAC encoding core with dynamic pipeline for H.264/AVC main profile. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2006. p. 760-763. 4145504 https://doi.org/10.1109/APCCAS.2006.342119
Li, Lingfeng ; Song, Yang ; Ikenaga, Takeshi ; Goto, Satoshi. / A CABAC encoding core with dynamic pipeline for H.264/AVC main profile. IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2006. pp. 760-763
@inproceedings{7859f03d4a734bbd8592d8ce2e4940b1,
title = "A CABAC encoding core with dynamic pipeline for H.264/AVC main profile",
abstract = "This paper presents an encoder core architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) in H.264/AVC main profile. The throughput of CABAC encoder is usually limited due to i) bit-wise processing, ii) complicated data dependency, and iii) variant iteration times for each binary symbol. This paper adopts dynamic pipeline scheme to improve the performance of CABAC encoder. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Meanwhile, pipeline bypass scheme is applied to eliminate the possible memory conflict Proposed encoder core is implemented under ROHM 0.35μm technology. Results show that the equivalent gate counts is 4.57k when the maximum frequency is 150MHz. It is estimated that the proposed CABAC encoding core can process the input binary symbol at a bit-rate of 80Mb/s.",
keywords = "Architecture, CABAC, H.264, Pipeline",
author = "Lingfeng Li and Yang Song and Takeshi Ikenaga and Satoshi Goto",
year = "2006",
doi = "10.1109/APCCAS.2006.342119",
language = "English",
isbn = "1424403871",
pages = "760--763",
booktitle = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

}

TY - GEN

T1 - A CABAC encoding core with dynamic pipeline for H.264/AVC main profile

AU - Li, Lingfeng

AU - Song, Yang

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2006

Y1 - 2006

N2 - This paper presents an encoder core architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) in H.264/AVC main profile. The throughput of CABAC encoder is usually limited due to i) bit-wise processing, ii) complicated data dependency, and iii) variant iteration times for each binary symbol. This paper adopts dynamic pipeline scheme to improve the performance of CABAC encoder. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Meanwhile, pipeline bypass scheme is applied to eliminate the possible memory conflict Proposed encoder core is implemented under ROHM 0.35μm technology. Results show that the equivalent gate counts is 4.57k when the maximum frequency is 150MHz. It is estimated that the proposed CABAC encoding core can process the input binary symbol at a bit-rate of 80Mb/s.

AB - This paper presents an encoder core architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) in H.264/AVC main profile. The throughput of CABAC encoder is usually limited due to i) bit-wise processing, ii) complicated data dependency, and iii) variant iteration times for each binary symbol. This paper adopts dynamic pipeline scheme to improve the performance of CABAC encoder. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Meanwhile, pipeline bypass scheme is applied to eliminate the possible memory conflict Proposed encoder core is implemented under ROHM 0.35μm technology. Results show that the equivalent gate counts is 4.57k when the maximum frequency is 150MHz. It is estimated that the proposed CABAC encoding core can process the input binary symbol at a bit-rate of 80Mb/s.

KW - Architecture

KW - CABAC

KW - H.264

KW - Pipeline

UR - http://www.scopus.com/inward/record.url?scp=48749128784&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=48749128784&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2006.342119

DO - 10.1109/APCCAS.2006.342119

M3 - Conference contribution

AN - SCOPUS:48749128784

SN - 1424403871

SN - 9781424403875

SP - 760

EP - 763

BT - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

ER -