A charge pump circuit without overstress in low-voltage CMOS standard process

Jun Pan; Tsutomu Yoshihara

doi:10.1109/EDSSC.2007.4450172

A charge pump circuit without overstress in low-voltage CMOS standard process

Jun Pan^*, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Citations (Scopus)

Abstract

An all PMOS charge pump circuit without over-stress is proposed in low-voltage standard process in this paper. The proposed circuit can reduce the equivalent on-resistancc of the charge-transfer transistors and can avoid the body effect due to the two pumping branches architecture. Therefore, its voltage pumping efficiency is much higher than that of the conventional designs. Moreover, the maximum gate-source, gate-drain and drain-source voltages of all transistors in the proposed charge pump circuit do not exceed the power supply voltage Vdd. The proposed charge pump circuit has been realized in a standard CMOS N-Well 0.35 μm technology. The measured results demonstrate that the proposed charge pump circuit has very high voltage pumping efficiency without overstress. Therefore, the proposed circuit is suitable for implementation in low-voltage CMOS standard process.

Original language	English
Title of host publication	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
Pages	501-504
Number of pages	4
DOIs	https://doi.org/10.1109/EDSSC.2007.4450172
Publication status	Published - 2007
Event	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan Duration: 2007 Dec 20 → 2007 Dec 22

Other

Other	IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
City	Tainan
Period	07/12/20 → 07/12/22

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/EDSSC.2007.4450172

Cite this

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title = "A charge pump circuit without overstress in low-voltage CMOS standard process",

abstract = "An all PMOS charge pump circuit without over-stress is proposed in low-voltage standard process in this paper. The proposed circuit can reduce the equivalent on-resistancc of the charge-transfer transistors and can avoid the body effect due to the two pumping branches architecture. Therefore, its voltage pumping efficiency is much higher than that of the conventional designs. Moreover, the maximum gate-source, gate-drain and drain-source voltages of all transistors in the proposed charge pump circuit do not exceed the power supply voltage Vdd. The proposed charge pump circuit has been realized in a standard CMOS N-Well 0.35 μm technology. The measured results demonstrate that the proposed charge pump circuit has very high voltage pumping efficiency without overstress. Therefore, the proposed circuit is suitable for implementation in low-voltage CMOS standard process.",

author = "Jun Pan and Tsutomu Yoshihara",

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doi = "10.1109/EDSSC.2007.4450172",

language = "English",

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pages = "501--504",

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AU - Pan, Jun

AU - Yoshihara, Tsutomu

PY - 2007

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N2 - An all PMOS charge pump circuit without over-stress is proposed in low-voltage standard process in this paper. The proposed circuit can reduce the equivalent on-resistancc of the charge-transfer transistors and can avoid the body effect due to the two pumping branches architecture. Therefore, its voltage pumping efficiency is much higher than that of the conventional designs. Moreover, the maximum gate-source, gate-drain and drain-source voltages of all transistors in the proposed charge pump circuit do not exceed the power supply voltage Vdd. The proposed charge pump circuit has been realized in a standard CMOS N-Well 0.35 μm technology. The measured results demonstrate that the proposed charge pump circuit has very high voltage pumping efficiency without overstress. Therefore, the proposed circuit is suitable for implementation in low-voltage CMOS standard process.

AB - An all PMOS charge pump circuit without over-stress is proposed in low-voltage standard process in this paper. The proposed circuit can reduce the equivalent on-resistancc of the charge-transfer transistors and can avoid the body effect due to the two pumping branches architecture. Therefore, its voltage pumping efficiency is much higher than that of the conventional designs. Moreover, the maximum gate-source, gate-drain and drain-source voltages of all transistors in the proposed charge pump circuit do not exceed the power supply voltage Vdd. The proposed charge pump circuit has been realized in a standard CMOS N-Well 0.35 μm technology. The measured results demonstrate that the proposed charge pump circuit has very high voltage pumping efficiency without overstress. Therefore, the proposed circuit is suitable for implementation in low-voltage CMOS standard process.

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A charge pump circuit without overstress in low-voltage CMOS standard process

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