A clocking scheme for lowering peak-current in dynamic logic circuits

Hiroyuki Matsubara, Takahiro Watanabe, Tadao Nakamura

Research output: Contribution to journalArticle

Abstract

This paper deals with a new low-power clocking scheme for dynamic logic circuits to reduce power dissipation. Although conventional clocking schemes for dynamic logic circuits are mainly used for high-speed applications like domino circuits, their peak-current are very large due to the concentration of precharging and discharging in a short period. It is hard for these schemes to accomplish both reductions of power dissipation and high performance at the same time. In the field of power engineering, leveling power means decreasing peak-topeak of power keeping its amount. So, we propose a sophisticated clocking scheme leveling power dissipation of processing elements that mainly reduces power dissipation of clock drivers. Our proposed clocking scheme uses an over-lapped clock with a fine-grain power control, and peak-current becomes lower and power dissipation in short period is leveled without penalty of speed performance. Our proposed scheme is applied to a 4-bit array multiplier, and reductions of power dissipation of both the multiplier and clock driver are measured by the HSPICE simulator based on 0.5 μm CMOS technology. It is shown that power dissipation of clock drivers, 4-bit array multiplier, and the total are reduced by about 13.2 percent, 2.6 percent and 7.0 percent, respectively. As a result, our clocking scheme is effective in reduction of power dissipations of clock drivers.

Original languageEnglish
Pages (from-to)1733-1738
Number of pages6
JournalIEICE Transactions on Electronics
VolumeE83-C
Issue number11
Publication statusPublished - 2000
Externally publishedYes

Fingerprint

Logic circuits
Energy dissipation
Clocks
Power control
Simulators
Networks (circuits)
Processing

Keywords

  • Dynamic logic
  • Leveling
  • Low-power
  • Over-lapped clock
  • Power control

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A clocking scheme for lowering peak-current in dynamic logic circuits. / Matsubara, Hiroyuki; Watanabe, Takahiro; Nakamura, Tadao.

In: IEICE Transactions on Electronics, Vol. E83-C, No. 11, 2000, p. 1733-1738.

Research output: Contribution to journalArticle

Matsubara, Hiroyuki ; Watanabe, Takahiro ; Nakamura, Tadao. / A clocking scheme for lowering peak-current in dynamic logic circuits. In: IEICE Transactions on Electronics. 2000 ; Vol. E83-C, No. 11. pp. 1733-1738.
@article{09c2ed981950438b8e6d0ee27e246d48,
title = "A clocking scheme for lowering peak-current in dynamic logic circuits",
abstract = "This paper deals with a new low-power clocking scheme for dynamic logic circuits to reduce power dissipation. Although conventional clocking schemes for dynamic logic circuits are mainly used for high-speed applications like domino circuits, their peak-current are very large due to the concentration of precharging and discharging in a short period. It is hard for these schemes to accomplish both reductions of power dissipation and high performance at the same time. In the field of power engineering, leveling power means decreasing peak-topeak of power keeping its amount. So, we propose a sophisticated clocking scheme leveling power dissipation of processing elements that mainly reduces power dissipation of clock drivers. Our proposed clocking scheme uses an over-lapped clock with a fine-grain power control, and peak-current becomes lower and power dissipation in short period is leveled without penalty of speed performance. Our proposed scheme is applied to a 4-bit array multiplier, and reductions of power dissipation of both the multiplier and clock driver are measured by the HSPICE simulator based on 0.5 μm CMOS technology. It is shown that power dissipation of clock drivers, 4-bit array multiplier, and the total are reduced by about 13.2 percent, 2.6 percent and 7.0 percent, respectively. As a result, our clocking scheme is effective in reduction of power dissipations of clock drivers.",
keywords = "Dynamic logic, Leveling, Low-power, Over-lapped clock, Power control",
author = "Hiroyuki Matsubara and Takahiro Watanabe and Tadao Nakamura",
year = "2000",
language = "English",
volume = "E83-C",
pages = "1733--1738",
journal = "IEICE Transactions on Electronics",
issn = "0916-8524",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "11",

}

TY - JOUR

T1 - A clocking scheme for lowering peak-current in dynamic logic circuits

AU - Matsubara, Hiroyuki

AU - Watanabe, Takahiro

AU - Nakamura, Tadao

PY - 2000

Y1 - 2000

N2 - This paper deals with a new low-power clocking scheme for dynamic logic circuits to reduce power dissipation. Although conventional clocking schemes for dynamic logic circuits are mainly used for high-speed applications like domino circuits, their peak-current are very large due to the concentration of precharging and discharging in a short period. It is hard for these schemes to accomplish both reductions of power dissipation and high performance at the same time. In the field of power engineering, leveling power means decreasing peak-topeak of power keeping its amount. So, we propose a sophisticated clocking scheme leveling power dissipation of processing elements that mainly reduces power dissipation of clock drivers. Our proposed clocking scheme uses an over-lapped clock with a fine-grain power control, and peak-current becomes lower and power dissipation in short period is leveled without penalty of speed performance. Our proposed scheme is applied to a 4-bit array multiplier, and reductions of power dissipation of both the multiplier and clock driver are measured by the HSPICE simulator based on 0.5 μm CMOS technology. It is shown that power dissipation of clock drivers, 4-bit array multiplier, and the total are reduced by about 13.2 percent, 2.6 percent and 7.0 percent, respectively. As a result, our clocking scheme is effective in reduction of power dissipations of clock drivers.

AB - This paper deals with a new low-power clocking scheme for dynamic logic circuits to reduce power dissipation. Although conventional clocking schemes for dynamic logic circuits are mainly used for high-speed applications like domino circuits, their peak-current are very large due to the concentration of precharging and discharging in a short period. It is hard for these schemes to accomplish both reductions of power dissipation and high performance at the same time. In the field of power engineering, leveling power means decreasing peak-topeak of power keeping its amount. So, we propose a sophisticated clocking scheme leveling power dissipation of processing elements that mainly reduces power dissipation of clock drivers. Our proposed clocking scheme uses an over-lapped clock with a fine-grain power control, and peak-current becomes lower and power dissipation in short period is leveled without penalty of speed performance. Our proposed scheme is applied to a 4-bit array multiplier, and reductions of power dissipation of both the multiplier and clock driver are measured by the HSPICE simulator based on 0.5 μm CMOS technology. It is shown that power dissipation of clock drivers, 4-bit array multiplier, and the total are reduced by about 13.2 percent, 2.6 percent and 7.0 percent, respectively. As a result, our clocking scheme is effective in reduction of power dissipations of clock drivers.

KW - Dynamic logic

KW - Leveling

KW - Low-power

KW - Over-lapped clock

KW - Power control

UR - http://www.scopus.com/inward/record.url?scp=33746364514&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33746364514&partnerID=8YFLogxK

M3 - Article

VL - E83-C

SP - 1733

EP - 1738

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 11

ER -