A clocking scheme for lowering peak-current in dynamic logic circuits

Hiroyuki Matsubara, Takahiro Watanabe, Tadao Nakamura

Research output: Contribution to journalArticle

Abstract

This paper deals with a new low-power clocking scheme for dynamic logic circuits to reduce power dissipation. Although conventional clocking schemes for dynamic logic circuits are mainly used for high-speed applications like domino circuits, their peak-current are very large due to the concentration of precharging and discharging in a short period. It is hard for these schemes to accomplish both reductions of power dissipation and high performance at the same time. In the field of power engineering, leveling power means decreasing peak-topeak of power keeping its amount. So, we propose a sophisticated clocking scheme leveling power dissipation of processing elements that mainly reduces power dissipation of clock drivers. Our proposed clocking scheme uses an over-lapped clock with a fine-grain power control, and peak-current becomes lower and power dissipation in short period is leveled without penalty of speed performance. Our proposed scheme is applied to a 4-bit array multiplier, and reductions of power dissipation of both the multiplier and clock driver are measured by the HSPICE simulator based on 0.5 μm CMOS technology. It is shown that power dissipation of clock drivers, 4-bit array multiplier, and the total are reduced by about 13.2 percent, 2.6 percent and 7.0 percent, respectively. As a result, our clocking scheme is effective in reduction of power dissipations of clock drivers.

Original languageEnglish
Pages (from-to)1733-1738
Number of pages6
JournalIEICE Transactions on Electronics
VolumeE83-C
Issue number11
Publication statusPublished - 2000 Jan 1

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Keywords

  • Dynamic logic
  • Leveling
  • Low-power
  • Over-lapped clock
  • Power control

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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