A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates

Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Abstract

In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process

Original languageEnglish
Title of host publicationProceedings - Design Automation Conference
Pages984-989
Number of pages6
Publication statusPublished - 2011
Externally publishedYes
Event2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 - San Diego, CA, United States
Duration: 2011 Jun 52011 Jun 9

Other

Other2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
CountryUnited States
CitySan Diego, CA
Period11/6/511/6/9

Fingerprint

Logic gates
Closed-form
Voltage
Logic
Combinatorial circuits
Electric potential
Threshold voltage
Transistors
Inverter
Square root
Logarithm
Silicon
Linear Function
Standard deviation
Networks (circuits)
Slope
Die
Monte Carlo Simulation
Directly proportional
Monte Carlo simulation

Keywords

  • Minimum operating voltage
  • subthreshold circuits
  • variations

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modelling and Simulation

Cite this

Fuketa, H., Iida, S., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., & Sakurai, T. (2011). A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates. In Proceedings - Design Automation Conference (pp. 984-989). [5981890]

A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates. / Fuketa, Hiroshi; Iida, Satoshi; Yasufuku, Tadashi; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu.

Proceedings - Design Automation Conference. 2011. p. 984-989 5981890.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fuketa, H, Iida, S, Yasufuku, T, Takamiya, M, Nomura, M, Shinohara, H & Sakurai, T 2011, A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates. in Proceedings - Design Automation Conference., 5981890, pp. 984-989, 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011, San Diego, CA, United States, 11/6/5.
Fuketa H, Iida S, Yasufuku T, Takamiya M, Nomura M, Shinohara H et al. A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates. In Proceedings - Design Automation Conference. 2011. p. 984-989. 5981890
Fuketa, Hiroshi ; Iida, Satoshi ; Yasufuku, Tadashi ; Takamiya, Makoto ; Nomura, Masahiro ; Shinohara, Hirofumi ; Sakurai, Takayasu. / A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates. Proceedings - Design Automation Conference. 2011. pp. 984-989
@inproceedings{f41212e4a0284f758afaaa21dcaeaf2f,
title = "A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates",
abstract = "In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11{\%} error. The expression is also verified with silicon measurements in a 65nm CMOS process",
keywords = "Minimum operating voltage, subthreshold circuits, variations",
author = "Hiroshi Fuketa and Satoshi Iida and Tadashi Yasufuku and Makoto Takamiya and Masahiro Nomura and Hirofumi Shinohara and Takayasu Sakurai",
year = "2011",
language = "English",
isbn = "9781450306362",
pages = "984--989",
booktitle = "Proceedings - Design Automation Conference",

}

TY - GEN

T1 - A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates

AU - Fuketa, Hiroshi

AU - Iida, Satoshi

AU - Yasufuku, Tadashi

AU - Takamiya, Makoto

AU - Nomura, Masahiro

AU - Shinohara, Hirofumi

AU - Sakurai, Takayasu

PY - 2011

Y1 - 2011

N2 - In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process

AB - In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process

KW - Minimum operating voltage

KW - subthreshold circuits

KW - variations

UR - http://www.scopus.com/inward/record.url?scp=80052658521&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052658521&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:80052658521

SN - 9781450306362

SP - 984

EP - 989

BT - Proceedings - Design Automation Conference

ER -