A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates

Hiroshi Fuketa; Satoshi Iida; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai

doi:10.1145/2024724.2024942

A closed-form expression for estimating minimum operating voltage (V _DDmin) of CMOS logic gates

Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

22 Citations (Scopus)

Abstract

In this paper, a closed-form expression for estimating a minimum operating voltage (V_DDmin) of CMOS logic gates is proposed. V_DDmin is defined as the minimum supply voltage at which circuits can operate correctly. V_DDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that V_DDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process

Original language	English
Title of host publication	2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	984-989
Number of pages	6
ISBN (Print)	9781450306362
DOIs	https://doi.org/10.1145/2024724.2024942
Publication status	Published - 2011 Jan 1

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

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Keywords

Minimum operating voltage
subthreshold circuits
variations

ASJC Scopus subject areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modelling and Simulation

Cite this

Fuketa, H., Iida, S., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., & Sakurai, T. (2011). A closed-form expression for estimating minimum operating voltage (V _DDmin) of CMOS logic gates. In 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 (pp. 984-989). [5981890] (Proceedings - Design Automation Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2024724.2024942

A closed-form expression for estimating minimum operating voltage (V _DDmin) of CMOS logic gates. / Fuketa, Hiroshi; Iida, Satoshi; Yasufuku, Tadashi; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu.

2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011. Institute of Electrical and Electronics Engineers Inc., 2011. p. 984-989 5981890 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fuketa, H, Iida, S, Yasufuku, T, Takamiya, M, Nomura, M, Shinohara, H & Sakurai, T 2011, A closed-form expression for estimating minimum operating voltage (V _DDmin) of CMOS logic gates. in 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011., 5981890, Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc., pp. 984-989. https://doi.org/10.1145/2024724.2024942

Fuketa H, Iida S, Yasufuku T, Takamiya M, Nomura M, Shinohara H et al. A closed-form expression for estimating minimum operating voltage (V _DDmin) of CMOS logic gates. In 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011. Institute of Electrical and Electronics Engineers Inc. 2011. p. 984-989. 5981890. (Proceedings - Design Automation Conference). https://doi.org/10.1145/2024724.2024942

Fuketa, Hiroshi ; Iida, Satoshi ; Yasufuku, Tadashi ; Takamiya, Makoto ; Nomura, Masahiro ; Shinohara, Hirofumi ; Sakurai, Takayasu. / A closed-form expression for estimating minimum operating voltage (V _DDmin) of CMOS logic gates. 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011. Institute of Electrical and Electronics Engineers Inc., 2011. pp. 984-989 (Proceedings - Design Automation Conference).

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Access to Document

10.1145/2024724.2024942