### Abstract

In this paper, a closed-form expression for estimating a minimum operating voltage (V_{DDmin}) of CMOS logic gates is proposed. V_{DDmin} is defined as the minimum supply voltage at which circuits can operate correctly. V_{DDmin} of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that V_{DDmin} of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process

Original language | English |
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Title of host publication | Proceedings - Design Automation Conference |

Pages | 984-989 |

Number of pages | 6 |

Publication status | Published - 2011 |

Externally published | Yes |

Event | 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 - San Diego, CA, United States Duration: 2011 Jun 5 → 2011 Jun 9 |

### Other

Other | 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 |
---|---|

Country | United States |

City | San Diego, CA |

Period | 11/6/5 → 11/6/9 |

### Fingerprint

### Keywords

- Minimum operating voltage
- subthreshold circuits
- variations

### ASJC Scopus subject areas

- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modelling and Simulation

### Cite this

_{DDmin}) of CMOS logic gates. In

*Proceedings - Design Automation Conference*(pp. 984-989). [5981890]

**A closed-form expression for estimating minimum operating voltage (V _{DDmin}) of CMOS logic gates.** / Fuketa, Hiroshi; Iida, Satoshi; Yasufuku, Tadashi; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

_{DDmin}) of CMOS logic gates. in

*Proceedings - Design Automation Conference.*, 5981890, pp. 984-989, 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011, San Diego, CA, United States, 11/6/5.

_{DDmin}) of CMOS logic gates. In Proceedings - Design Automation Conference. 2011. p. 984-989. 5981890

}

TY - GEN

T1 - A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates

AU - Fuketa, Hiroshi

AU - Iida, Satoshi

AU - Yasufuku, Tadashi

AU - Takamiya, Makoto

AU - Nomura, Masahiro

AU - Shinohara, Hirofumi

AU - Sakurai, Takayasu

PY - 2011

Y1 - 2011

N2 - In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process

AB - In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process

KW - Minimum operating voltage

KW - subthreshold circuits

KW - variations

UR - http://www.scopus.com/inward/record.url?scp=80052658521&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052658521&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:80052658521

SN - 9781450306362

SP - 984

EP - 989

BT - Proceedings - Design Automation Conference

ER -